APAC 2007, session 7 "Accelerator Technology"
Lawrence Doolittle, LBNL
RRCAT, Indore, India, Jan 28 - Feb 2, 2007
Low-level RF (LLRF) control hardware and its embedded programming plays a pivotal role in the performance of an accelerator. Modern designs implement most of the signal processing in the digital domain. This reduces the size and cost of the hardware, but places the burden of proper operation on the programming. FPGAs (field programmable gate arrays) and communications-grade ADCs and DACs enable sub-microsecond delay for the LLRF controller feedback signal. Ancient concepts of the virtue of simplicity are easy to apply to the hardware, but more of a challenge in the context of programming. Digital signal processing, combined with dedicated hardware, can control and maintain cavity phase (relative to an absolute reference) unaffected by drift or 1/f noise of any long cables or active components. Developing and testing that programming is a very real challenge. This paper discusses approaches and techniques to make LLRF systems meet their goals in upcoming accelerators.
Talk (HTML), and translations courtesy of Google:
The HTML version above includes my notes about what to talk about, and is intended to stand on its own. Here is the PDF with the slides alone, but be warned they are rather cryptic without me there to explain them.