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Signals index

D
 D : SRL16E : input
Connects up to:srl16x19e:d0:D , srl16x19e:d1:D , srl16x19e:d2:D , srl16x19e:d3:D , srl16x19e:d4:D , srl16x19e:d5:D , srl16x19e:d6:D , srl16x19e:d7:D , srl16x19e:d8:D , srl16x19e:d9:D , srl16x19e:d10:D , srl16x19e:d11:D , srl16x19e:d12:D , srl16x19e:d13:D , srl16x19e:d14:D , srl16x19e:d15:D , srl16x19e:d16:D , srl16x19e:d17:D , srl16x19e:d18:D , srl16x4e:d0:D , srl16x4e:d1:D , srl16x4e:d2:D , srl16x4e:d3:D , srl16x16e:d0:D , srl16x16e:d1:D , srl16x16e:d2:D , srl16x16e:d3:D , srl16x16e:d4:D , srl16x16e:d5:D , srl16x16e:d6:D , srl16x16e:d7:D , srl16x16e:d8:D , srl16x16e:d9:D , srl16x16e:d10:D , srl16x16e:d11:D , srl16x16e:d12:D , srl16x16e:d13:D , srl16x16e:d14:D , srl16x16e:d15:D , srl16x22e:d0:D , srl16x22e:d1:D , srl16x22e:d2:D , srl16x22e:d3:D , srl16x22e:d4:D , srl16x22e:d5:D , srl16x22e:d6:D , srl16x22e:d7:D , srl16x22e:d8:D , srl16x22e:d9:D , srl16x22e:d10:D , srl16x22e:d11:D , srl16x22e:d12:D , srl16x22e:d13:D , srl16x22e:d14:D , srl16x22e:d15:D , srl16x22e:d16:D , srl16x22e:d17:D , srl16x22e:d18:D , srl16x22e:d19:D , srl16x22e:d20:D , srl16x22e:d21:D 
 D : srl16x16e : input wire
Connects down to:SRL16E:d0:D , SRL16E:d1:D , SRL16E:d2:D , SRL16E:d3:D , SRL16E:d4:D , SRL16E:d5:D , SRL16E:d6:D , SRL16E:d7:D , SRL16E:d8:D , SRL16E:d9:D , SRL16E:d10:D , SRL16E:d11:D , SRL16E:d12:D , SRL16E:d13:D , SRL16E:d14:D , SRL16E:d15:D 
Connects up to:dkcm_bussed:bank0:load_data , dkcm_bussed:bank1:load_data , dkcm_bussed:bank2:load_data , totalizer:s2:load_data 
 D : srl16x19e : input wire
Connects down to:SRL16E:d0:D , SRL16E:d1:D , SRL16E:d2:D , SRL16E:d3:D , SRL16E:d4:D , SRL16E:d5:D , SRL16E:d6:D , SRL16E:d7:D , SRL16E:d8:D , SRL16E:d9:D , SRL16E:d10:D , SRL16E:d11:D , SRL16E:d12:D , SRL16E:d13:D , SRL16E:d14:D , SRL16E:d15:D , SRL16E:d16:D , SRL16E:d17:D , SRL16E:d18:D 
Connects up to:hist2:fifo:sum 
 D : srl16x22e : input wire
Connects down to:SRL16E:d0:D , SRL16E:d1:D , SRL16E:d2:D , SRL16E:d3:D , SRL16E:d4:D , SRL16E:d5:D , SRL16E:d6:D , SRL16E:d7:D , SRL16E:d8:D , SRL16E:d9:D , SRL16E:d10:D , SRL16E:d11:D , SRL16E:d12:D , SRL16E:d13:D , SRL16E:d14:D , SRL16E:d15:D , SRL16E:d16:D , SRL16E:d17:D , SRL16E:d18:D , SRL16E:d19:D , SRL16E:d20:D , SRL16E:d21:D 
Connects up to:totalizer:s1:load_data 
 D : srl16x4e : input wire
Connects down to:SRL16E:d0:D , SRL16E:d1:D , SRL16E:d2:D , SRL16E:d3:D 
Connects up to:stopwatch:counter:count_hi , stopwatch:memory:count_hi 
 DA : history2e : input
Connects up to:llrf_interim:history2e:DA 
 DA : llrf_interim : input
Connects down to:history2e:history2e:DA 
 dal : history2e : reg
 dals : history2e : wire
 DAOV : llrf_interim : input
Connects down to:route_interim:route_interim:DAOV 
 DAOV : route_interim : input
Connects up to:llrf_interim:route_interim:DAOV 
 daov_ : llrf_interim : wire
Connects down to:route_interim:route_interim:daov_ , status:status:daov_ 
 daov_ : route_interim : output
Connects up to:llrf_interim:route_interim:daov_ 
 daov_ : status : input
Connects up to:llrf_interim:status:daov_ 
 daov_latch : status : reg
 data : config_romx : output reg
Connects up to:config_rom:rom:low_byte 
 data : sportx : output reg
Connects up to:llrf_interim:sportx:sportx__data 
 data : SRL16E : reg
 daverage : history2e : wire
Connects down to:hist2:traced:average , histmode:dhm:average 
 davg_clear : history2e : wire
Connects down to:hist2:traced:clear , histmode:dhm:avg_clear 
 DB : history2e : input
Connects up to:llrf_interim:history2e:DB 
 DB : llrf_interim : input
Connects down to:history2e:history2e:DB 
 dbl : history2e : reg
 dbls : history2e : wire
 DBOV : llrf_interim : input
Connects down to:route_interim:route_interim:DBOV 
 DBOV : route_interim : input
Connects up to:llrf_interim:route_interim:DBOV 
 dbov_ : llrf_interim : wire
Connects down to:route_interim:route_interim:dbov_ , status:status:dbov_ 
 dbov_ : route_interim : output
Connects up to:llrf_interim:route_interim:dbov_ 
 dbov_ : status : input
Connects up to:llrf_interim:status:dbov_ 
 dbov_latch : status : reg
 DC : history2e : input
Connects up to:llrf_interim:history2e:DC 
 DC : llrf_interim : input
Connects down to:history2e:history2e:DC 
 dcl : history2e : reg
 dcls : history2e : wire
 dcnt_at_pulse_end : history2e : output
Connects down to:histmode:dhm:cnt_at_pulse_end 
Connects up to:llrf_interim:history2e:history2e__dcnt_at_pulse_end 
 DCOV : llrf_interim : input
Connects down to:route_interim:route_interim:DCOV 
 DCOV : route_interim : input
Connects up to:llrf_interim:route_interim:DCOV 
 dcov_ : llrf_interim : wire
Connects down to:route_interim:route_interim:dcov_ , status:status:dcov_ 
 dcov_ : route_interim : output
Connects up to:llrf_interim:route_interim:dcov_ 
 dcov_ : status : input
Connects up to:llrf_interim:status:dcov_ 
 dcov_latch : status : reg
 DD : history2e : input
Connects up to:llrf_interim:history2e:DD 
 DD : llrf_interim : input
Connects down to:history2e:history2e:DD 
 ddl : history2e : reg
 ddls : history2e : wire
 DDOV : llrf_interim : input
Connects down to:route_interim:route_interim:DDOV 
 DDOV : route_interim : input
Connects up to:llrf_interim:route_interim:DDOV 
 ddov_ : llrf_interim : wire
Connects down to:route_interim:route_interim:ddov_ , status:status:ddov_ 
 ddov_ : route_interim : output
Connects up to:llrf_interim:route_interim:ddov_ 
 ddov_ : status : input
Connects up to:llrf_interim:status:ddov_ 
 ddov_latch : status : reg
 dds_passthru : rf_timer : wire
 dds_run : dds : input
Connects up to:llrf_interim:dds:dds_run 
 dds_run : llrf_interim : wire
Connects down to:dds:dds:dds_run , rf_timer:rf_timer:dds_run 
 dds_run : rf_timer : output
Connects up to:llrf_interim:rf_timer:dds_run 
 dds_substitute : fdbk_loop : input
Connects up to:llrf_interim:fdbk_loop:dds_substitute 
 dds_substitute : llrf_interim : wire
Connects down to:rf_timer:rf_timer:dds_substitute , fdbk_loop:fdbk_loop:dds_substitute 
 dds_substitute : rf_timer : output
Connects up to:llrf_interim:rf_timer:dds_substitute 
 dds__freq : llrf_interim : reg
Connects down to:dds:dds:freq 
 dds__set_i : llrf_interim : reg
Connects down to:dds:dds:set_i 
 dds__set_q : llrf_interim : reg
Connects down to:dds:dds:set_q 
 DE : afterburner : output
Connects up to:llrf_interim:afterburner:DE 
 DE : llrf_interim : output
Connects down to:afterburner:afterburner:DE 
 devsel : sportx : reg
 dhistory_config : history2e : input
Connects up to:llrf_interim:history2e:history2e__dhistory_config 
 DIA : RAMB4_S8_S8 : input
Connects up to:ramdp512x16:b0:DIA , ramdp512x16:b1:DIA 
 DIA : ramdp512x16 : input wire
Connects down to:RAMB4_S8_S8:b0:DIA , RAMB4_S8_S8:b1:DIA 
Connects up to:hist2:trace1:keep 
 DIB : RAMB4_S8_S8 : input
Connects up to:feedforward:feedforward_table:host_data , ramdp512x16:b0:DIB , ramdp512x16:b1:DIB 
 DIB : ramdp512x16 : input wire
Connects down to:RAMB4_S8_S8:b0:DIB , RAMB4_S8_S8:b1:DIB 
 DIO1 : llrf_interim : output
Connects down to:route_interim:route_interim:DIO1 
 DIO1 : route_interim : output
Connects up to:llrf_interim:route_interim:DIO1 
 DIO2 : llrf_interim : output
Connects down to:route_interim:route_interim:DIO2 
 DIO2 : route_interim : output
Connects up to:llrf_interim:route_interim:DIO2 
 DIO3 : llrf_interim : output
Connects down to:route_interim:route_interim:DIO3 
 DIO3 : route_interim : output
Connects up to:llrf_interim:route_interim:DIO3 
 DIO4 : llrf_interim : output
Connects down to:route_interim:route_interim:DIO4 
 DIO4 : route_interim : output
Connects up to:llrf_interim:route_interim:DIO4 
 DIO6 : llrf_interim : output
Connects down to:route_interim:route_interim:DIO6 
 DIO6 : route_interim : output
Connects up to:llrf_interim:route_interim:DIO6 
 divider : ds2401_driver : reg
 divider : sportx : reg
 dkcm_bus : afterburner : input
Connects down to:dkcm_bussed:scale:dkcm_bus 
Connects up to:llrf_interim:afterburner:dkcm_bus 
 dkcm_bus : dkcm_bussed : input
Connects up to:afterburner:scale:dkcm_bus , fdbk_loop:MUL1:dkcm_bus , fdbk_loop:MUL2:dkcm_bus , fdbk_loop:MUL3:dkcm_bus 
 dkcm_bus : dkcm_controller : output
Connects up to:llrf_interim:dkcm_controller:dkcm_bus 
 dkcm_bus : fdbk_loop : input
Connects down to:dkcm_bussed:MUL1:dkcm_bus , dkcm_bussed:MUL2:dkcm_bus , dkcm_bussed:MUL3:dkcm_bus 
Connects up to:llrf_interim:fdbk_loop:dkcm_bus 
 dkcm_bus : llrf_interim : wire
Connects down to:dkcm_controller:dkcm_controller:dkcm_bus , fdbk_loop:fdbk_loop:dkcm_bus , afterburner:afterburner:dkcm_bus 
 dkcm_busy : dkcm_controller : output
Connects up to:llrf_interim:dkcm_controller:dkcm_busy 
 dkcm_busy : llrf_interim : wire
Connects down to:dkcm_controller:dkcm_controller:dkcm_busy , status:status:dkcm_busy 
 dkcm_busy : status : input
Connects up to:llrf_interim:status:dkcm_busy 
 dkcm_controller__select : llrf_interim : wire
Connects down to:dkcm_controller:dkcm_controller:select 
 DOA : RAMB4_S8_S8 : output reg
Connects up to:feedforward:feedforward_table:feedforward_raw , ramdp512x16:b0:DOA , ramdp512x16:b1:DOA 
 DOA : ramdp512x16 : output wire
Connects down to:RAMB4_S8_S8:b0:DOA , RAMB4_S8_S8:b1:DOA 
 DOB : RAMB4_S8_S8 : output reg
Connects up to:feedforward:feedforward_table:host_dout , ramdp512x16:b0:DOB , ramdp512x16:b1:DOB 
 DOB : ramdp512x16 : output wire
Connects down to:RAMB4_S8_S8:b0:DOB , RAMB4_S8_S8:b1:DOB 
Connects up to:hist2:trace1:host_dout 
 dout : sportx : reg
 dout : totalizer : output
Connects down to:srl16x16e:s2:Q 
Connects up to:llrf_interim:totalizer:totalizer__dout 
 DOUT1202 : llrf_interim : input
Connects down to:sportx:sportx:DOUT1202 
 DOUT1202 : sportx : input
Connects up to:llrf_interim:sportx:DOUT1202 
 dphase : dds : wire
 drive : ds2401_driver : reg
 DS2401 : ds2401_driver : inout
Connects up to:llrf_interim:ds2401_driver:DS2401 
 DS2401 : llrf_interim : inout
Connects down to:ds2401_driver:ds2401_driver:DS2401 
 ds2401_driver__read_bus : llrf_interim : wire
Connects down to:ds2401_driver:ds2401_driver:read_bus 
 ds2401_driver__select : llrf_interim : wire
Connects down to:ds2401_driver:ds2401_driver:select 
 dstop_count : history2e : input
Connects down to:histmode:dhm:stop_count 
Connects up to:llrf_interim:history2e:history2e__dstop_count 
 dtrace_address : history2e : wire
Connects down to:hist2:traced:trace_address , histmode:dhm:trace_address 
 dwrite_enable : history2e : wire
Connects down to:hist2:traced:write_enable , histmode:dhm:write_enable 
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Created:Wed May 19 11:23:08 2004
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