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| A | B | C | D | E | F | G | H | I | K | L | M | O | P | Q | R | S | T | U | V | W | X | Y | Z |
| I |
| Connects up to: | afterburner:u5:CLK80X , nanoengine_if:u3:clk_hack , route_interim:u1:CLK |
| Connects up to: | nanoengine_if:u4:CK_host |
| Connects down to: | route_interim:route_interim:IL_STAT |
| Connects up to: | llrf_interim:route_interim:IL_STAT |
| Connects down to: | route_interim:route_interim:il_stat_ , status:status:il_stat_ |
| Connects up to: | llrf_interim:route_interim:il_stat_ |
| Connects up to: | llrf_interim:status:il_stat_ |
| Connects up to: | llrf_interim:fdbk_loop:integrate_enable |
| Connects down to: | rf_timer:rf_timer:integrate_enable , fdbk_loop:fdbk_loop:integrate_enable |
| Connects up to: | llrf_interim:rf_timer:integrate_enable |
| Connects down to: | nanoengine_if:nanoengine_if:INT_host |
| Connects up to: | llrf_interim:nanoengine_if:INT_host |
| Connects up to: | history2e:traced:traced_data , history2e:trace2:trace2_data , history2e:trace1:trace1_data , history2e:trace3:trace3_data |
| K |
| Connects down to: | ramdp512x16:trace1:DIA |
| L |
| Connects up to: | status:flasher:LED2 |
| Connects down to: | status:status:LED2 |
| Connects down to: | flasher:flasher:lampo |
| Connects up to: | llrf_interim:status:LED2 |
| Connects down to: | rf_timer:rf_timer:LED3 |
| Connects up to: | llrf_interim:rf_timer:LED3 |
| Connects down to: | rf_timer:rf_timer:LED4 |
| Connects up to: | llrf_interim:rf_timer:LED4 |
| Connects down to: | srl16x16e:bank0:D , srl16x16e:bank1:D , srl16x16e:bank2:D |
| Connects down to: | srl16x22e:s1:D , srl16x16e:s2:D |
| Connects down to: | srl16x16e:bank2:CE |
| Connects down to: | srl16x16e:bank0:CE , srl16x16e:bank1:CE |
| Connects down to: | RAMB4_S8_S8:feedforward_table:WEB |
| Connects down to: | config_romx:rom:data |
| Connects down to: | route_interim:route_interim:lrc_slot , status:status:lrc_slot |
| Connects up to: | llrf_interim:route_interim:lrc_slot |
| Connects up to: | llrf_interim:status:lrc_slot |
| M |
| O |
| Connects up to: | afterburner:u5:clk80 , nanoengine_if:u3:host_clk , route_interim:u1:clk40 |
| Connects up to: | nanoengine_if:u4:clk_hack |
| Connects up to: | llrf_interim:afterburner:outsig40 |
| Connects up to: | llrf_interim:fdbk_loop:outsig40 |
| Connects up to: | llrf_interim:history2e:outsig40 |
| Connects down to: | history2e:history2e:outsig40 , fdbk_loop:fdbk_loop:outsig40 , afterburner:afterburner:outsig40 |
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| This page: | Maintained by: | ldoolitt@recycle.lbl.gov |
| Created: | Wed May 19 11:23:09 2004 |
| Verilog converted to html by v2html 7.30 (written by Costas Calamvokis). | Help |