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| S |
| Connects down to: | srl16x4e:memory:CE |
| Connects down to: | sportx:sportx:SCLK |
| Connects up to: | llrf_interim:sportx:SCLK |
| Connects down to: | sportx:sportx:SDA75 |
| Connects up to: | llrf_interim:sportx:SDA75 |
| Connects down to: | sportx:sportx:SDIN |
| Connects up to: | llrf_interim:sportx:SDIN |
| Connects up to: | llrf_interim:dkcm_controller:dkcm_controller__select |
| Connects up to: | llrf_interim:ds2401_driver:ds2401_driver__select |
| Connects up to: | llrf_interim:feedforward:feedforward__select |
| Connects up to: | llrf_interim:shadow_ram:shadow_ram__select |
| Connects up to: | llrf_interim:sportx:sportx__select_cntl |
| Connects up to: | llrf_interim:sportx:sportx__select_data |
| Connects down to: | cordic:c:xin |
| Connects up to: | llrf_interim:dds:dds__set_i |
| Connects down to: | cordic:c:yin |
| Connects up to: | llrf_interim:dds:dds__set_q |
| Connects down to: | cordic:c:xout |
| Connects up to: | llrf_interim:dds:set_wave |
| Connects up to: | llrf_interim:fdbk_loop:set_wave |
| Connects down to: | dds:dds:set_wave , fdbk_loop:fdbk_loop:set_wave |
| Connects down to: | shadow_ram:shadow_ram:read_bus |
| Connects down to: | shadow_ram:shadow_ram:select |
| Connects down to: | addsub:ax:b , addsub:ax:b , addsub:ay:b , addsub:ay:b |
| Connects down to: | route_interim:route_interim:SLEEP |
| Connects up to: | llrf_interim:route_interim:SLEEP |
| Connects down to: | sportx:sportx:data |
| Connects down to: | sportx:sportx:select_cntl |
| Connects down to: | sportx:sportx:select_data |
| Connects down to: | sportx:sportx:status |
| Connects up to: | llrf_interim:sportx:sportx__status |
| Connects up to: | llrf_interim:status:status__status |
| Connects down to: | status:status:errors |
| Connects down to: | status:status:error_en |
| Connects down to: | status:status:status |
| Connects down to: | stopwatch:stopwatch:control_sel |
| Connects down to: | stopwatch:stopwatch:readout |
| Connects up to: | history2e:uhm:ustop_count , history2e:dhm:dstop_count |
| Connects up to: | cstage:az:zout , cstage:ax:xout , cstage:ay:yout , cordic:az1:zw1 , cordic:ay0:yw0 , cordic:ay1:yw1 , cordic:ax0:xw0 , cordic:ax1:xw1 |
| Connects down to: | srl16x19e:fifo:D |
| Connects down to: | sync_free:sync_free:sync_error , status:status:sync_error |
| Connects up to: | llrf_interim:status:sync_error |
| Connects up to: | llrf_interim:sync_free:sync_error |
| Connects down to: | sync_free:sync_free:sync_missing , status:status:sync_missing |
| Connects up to: | llrf_interim:status:sync_missing |
| Connects up to: | llrf_interim:sync_free:sync_missing |
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| This page: | Maintained by: | ldoolitt@recycle.lbl.gov |
| Created: | Wed May 19 11:23:09 2004 |
| Verilog converted to html by v2html 7.30 (written by Costas Calamvokis). | Help |