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// automatically generated by
//  perl intercon.pl ../source/register-map ../source/nanoengine_if.v ../source/route_mebt.v ../source/config_rom.v ../source/sport.v ../source/dds.v ../source/sync_mebt.v ../source/shadow_ram.v ../source/totalizer.v ../source/feedforward.v ../source/rf_timer.v ../source/history2e.v ../source/dkcm_controller.v ../source/fdbk_loop.v ../source/afterdemux.v ../source/status.v ../source/stopwatch.v -o llrf_mebt.v
// processing file ../source/nanoengine_if.v
// processing file ../source/route_mebt.v
// processing file ../source/config_rom.v
// processing file ../source/sport.v
// processing file ../source/dds.v
// processing file ../source/sync_mebt.v
// processing file ../source/shadow_ram.v
// processing file ../source/totalizer.v
// processing file ../source/feedforward.v
// processing file ../source/rf_timer.v
// processing file ../source/history2e.v
// processing file ../source/dkcm_controller.v
// processing file ../source/fdbk_loop.v
// processing file ../source/afterdemux.v
// processing file ../source/status.v
// processing file ../source/stopwatch.v

`timescale 1ns / 1ns

module llrf_mebtIndex(
// module nanoengine_if
	inout [15:0] PD,
	input CK_host,
	input ALE_host,
	input WE_host,
	input RD_host,
	input CS0_host,
	output RDY_host,
	output INT_host,
// module route_mebt
	input CLK,
	input DAOV,
	input DBOV,
	input DCOV,
	input DDOV,
	output P_DOWN,
	input RF_ON,
	output LED1,
	output RF_KILL,
	output SLEEP,
// module sport
	output SP_SCLK,
	output SP_DIN,
	input SP_DOUT,
	output SP_CS0,
	output SP_CS1,
	output SP_CS2,
	output SP_CS3,
// module sync_mebt
	input SYNC,
// module rf_timer
	output LED3,
	output LED4,
// module history2e
	input [`RAW_ADC_BITS-1:0] DA,
	input [`RAW_ADC_BITS-1:0] DB,
	input [`RAW_ADC_BITS-1:0] DC,
	input [`RAW_ADC_BITS-1:0] DD,
// module afterdemux
	output [11:0] DE,
	output OCLK,
	output OSEL,
// module status
	output LED2
);

// wires:
wire        clk40;                        //  route_mebt dds sync_mebt totalizer feedforward rf_timer history2e fdbk_loop afterdemux status stopwatch
wire        clk40_missing_pulse;          //  status
wire [15:0] config_rom__read_bus;         // to read mux
wire        daov_;                        //  route_mebt status
wire        dbov_;                        //  route_mebt status
wire        dcov_;                        //  route_mebt status
wire        ddov_;                        //  route_mebt status
wire        dds_run;                      //  dds rf_timer
wire        dds_substitute;               //  rf_timer fdbk_loop
wire [21:0] dkcm_bus;                     //  dkcm_controller fdbk_loop
wire        dkcm_busy;                    //  dkcm_controller status
wire        dkcm_controller__select;      // select
wire [13:0] fdbk_input;                   //  history2e fdbk_loop
wire        feedback_enable;              //  rf_timer fdbk_loop
wire [15:0] feedforward__host_dout;       // to read mux
wire        feedforward__select;          // select
wire [12:0] feedforward_data;             //  feedforward fdbk_loop
wire        feedforward_start;            //  feedforward rf_timer
wire [14:0] history2e__dcnt_at_pulse_end; // to read mux
wire [15:0] history2e__trace1_dout;       // to read mux
wire [15:0] history2e__trace2_dout;       // to read mux
wire [15:0] history2e__trace3_dout;       // to read mux
wire [15:0] history2e__traced_dout;       // to read mux
wire [14:0] history2e__ucnt_at_pulse_end; // to read mux
wire [13:0] host_addr;                    //  nanoengine_if config_rom sport shadow_ram totalizer feedforward rf_timer history2e dkcm_controller stopwatch
wire        host_clk;                     //  nanoengine_if sport shadow_ram feedforward rf_timer history2e dkcm_controller fdbk_loop afterdemux status stopwatch
wire [15:0] host_data;                    //  nanoengine_if sport shadow_ram feedforward rf_timer dkcm_controller status stopwatch
wire        host_interrupt;               //  nanoengine_if rf_timer
wire        host_re;                      //  nanoengine_if status
wire [15:0] host_read;                    //  nanoengine_if
wire        host_we;                      //  nanoengine_if sport shadow_ram feedforward rf_timer dkcm_controller status stopwatch
wire        il_stat_;                     //  route_mebt status
wire        integrate_enable;             //  rf_timer fdbk_loop
wire  [1:0] lrc_slot;                     //  route_mebt status
wire [11:0] outsig40;                     //  history2e fdbk_loop afterdemux
wire        phase_sense_adjust;           //  sync_mebt rf_timer
wire        pll_muxout_;                  //  status
wire        power_down;                   //  route_mebt rf_timer
wire        quad_sync;                    //  sync_mebt rf_timer
wire        rf_kill_;                     //  route_mebt rf_timer
wire        rf_on_;                       //  route_mebt rf_timer
wire        rf_on_sync;                   //  rf_timer status stopwatch
wire [15:0] rf_timer__host_read;          // to read mux
wire        rf_timer__hselect;            // select
wire        rst;                          //  nanoengine_if sport totalizer rf_timer history2e
wire [15:0] set_wave;                     //  dds fdbk_loop
wire [15:0] shadow_ram__read_bus;         // to read mux
wire        shadow_ram__select;           // select
wire        sport__hselect;               // select
wire [15:0] sport__odata;                 // to read mux
wire        status__error_en;             // select
wire [15:0] status__errors;               // to read mux
wire [15:0] status__status;               // to read mux
wire        stopwatch__control_sel;       // select
wire [15:0] stopwatch__readout;           // to read mux
wire        sync_error;                   //  sync_mebt status
wire        sync_missing;                 //  sync_mebt status
wire [15:0] totalizer__dout;              // to read mux
wire        totalizer_channel;            //  rf_timer history2e
wire        totalizer_gate;               //  totalizer rf_timer
wire [13:0] totalizer_in;                 //  totalizer history2e
wire        trace_enable;                 //  rf_timer history2e status
wire        trigger_skipped;              //  rf_timer status

// regs:
reg [15:0] dds__set_i;
reg [15:0] dds__set_q;
reg [15:0] dds__freq;
reg [15:0] rf_timer__totalizer_delay;
reg [15:0] rf_timer__config_word;
reg [14:0] history2e__ustop_count;
reg [15:0] history2e__uhistory_config;
reg [14:0] history2e__dstop_count;
reg [15:0] history2e__dhistory_config;
reg [15:0] afterdemux__mode_control;

// instantiations:
nanoengine_if nanoengine_if(
	.PD(PD),
	.CK_host(CK_host),
	.ALE_host(ALE_host),
	.WE_host(WE_host),
	.RD_host(RD_host),
	.CS0_host(CS0_host),
	.RDY_host(RDY_host),
	.INT_host(INT_host),
	.host_clk(host_clk),
	.host_addr(host_addr),
	.host_data(host_data),
	.host_read(host_read),
	.host_we(host_we),
	.host_re(host_re),
	.rst(rst),
	.host_interrupt(host_interrupt)
);
route_mebt route_mebt(
	.CLK(CLK),
	.clk40(clk40),
	.DAOV(DAOV),
	.DBOV(DBOV),
	.DCOV(DCOV),
	.DDOV(DDOV),
	.daov_(daov_),
	.dbov_(dbov_),
	.dcov_(dcov_),
	.ddov_(ddov_),
	.lrc_slot(lrc_slot),
	.il_stat_(il_stat_),
	.power_down(power_down),
	.P_DOWN(P_DOWN),
	.RF_ON(RF_ON),
	.rf_on_(rf_on_),
	.LED1(LED1),
	.rf_kill_(rf_kill_),
	.RF_KILL(RF_KILL),
	.SLEEP(SLEEP)
);
config_rom config_rom(
	.host_addr(host_addr),
	.read_bus(config_rom__read_bus)
);
sport sport(
	.rst(rst),
	.host_clk(host_clk),
	.host_addr(host_addr),
	.host_we(host_we),
	.host_data(host_data),
	.odata(sport__odata),
	.hselect(sport__hselect),
	.SP_SCLK(SP_SCLK),
	.SP_DIN(SP_DIN),
	.SP_DOUT(SP_DOUT),
	.SP_CS0(SP_CS0),
	.SP_CS1(SP_CS1),
	.SP_CS2(SP_CS2),
	.SP_CS3(SP_CS3)
);
dds dds(
	.set_i(dds__set_i),
	.set_q(dds__set_q),
	.freq(dds__freq),
	.clk40(clk40),
	.dds_run(dds_run),
	.set_wave(set_wave)
);
sync_mebt sync_mebt(
	.SYNC(SYNC),
	.clk40(clk40),
	.phase_sense_adjust(phase_sense_adjust),
	.quad_sync(quad_sync),
	.sync_error(sync_error),
	.sync_missing(sync_missing)
);
shadow_ram shadow_ram(
	.host_clk(host_clk),
	.host_we(host_we),
	.host_addr(host_addr),
	.select(shadow_ram__select),
	.host_data(host_data),
	.read_bus(shadow_ram__read_bus)
);
totalizer totalizer(
	.host_addr(host_addr),
	.dout(totalizer__dout),
	.totalizer_in(totalizer_in),
	.rst(rst),
	.clk40(clk40),
	.totalizer_gate(totalizer_gate)
);
feedforward feedforward(
	.host_clk(host_clk),
	.host_addr(host_addr),
	.host_we(host_we),
	.host_data(host_data),
	.host_dout(feedforward__host_dout),
	.select(feedforward__select),
	.clk40(clk40),
	.feedforward_start(feedforward_start),
	.feedforward_data(feedforward_data)
);
rf_timer rf_timer(
	.rst(rst),
	.host_clk(host_clk),
	.host_addr(host_addr),
	.host_we(host_we),
	.host_data(host_data),
	.host_read(rf_timer__host_read),
	.hselect(rf_timer__hselect),
	.clk40(clk40),
	.quad_sync(quad_sync),
	.rf_on_sync(rf_on_sync),
	.totalizer_delay(rf_timer__totalizer_delay),
	.config_word(rf_timer__config_word),
	.feedback_enable(feedback_enable),
	.integrate_enable(integrate_enable),
	.feedforward_start(feedforward_start),
	.host_interrupt(host_interrupt),
	.trace_enable(trace_enable),
	.trigger_skipped(trigger_skipped),
	.totalizer_gate(totalizer_gate),
	.dds_run(dds_run),
	.dds_substitute(dds_substitute),
	.totalizer_channel(totalizer_channel),
	.phase_sense_adjust(phase_sense_adjust),
	.rf_on_(rf_on_),
	.rf_kill_(rf_kill_),
	.power_down(power_down),
	.LED3(LED3),
	.LED4(LED4)
);
history2e history2e(
	.rst(rst),
	.host_clk(host_clk),
	.host_addr(host_addr),
	.traced_dout(history2e__traced_dout),
	.trace1_dout(history2e__trace1_dout),
	.trace2_dout(history2e__trace2_dout),
	.trace3_dout(history2e__trace3_dout),
	.clk40(clk40),
	.DA(DA),
	.DB(DB),
	.DC(DC),
	.DD(DD),
	.outsig40(outsig40),
	.fdbk_input(fdbk_input),
	.totalizer_channel(totalizer_channel),
	.totalizer_in(totalizer_in),
	.ustop_count(history2e__ustop_count),
	.uhistory_config(history2e__uhistory_config),
	.dstop_count(history2e__dstop_count),
	.dhistory_config(history2e__dhistory_config),
	.ucnt_at_pulse_end(history2e__ucnt_at_pulse_end),
	.dcnt_at_pulse_end(history2e__dcnt_at_pulse_end),
	.trace_enable(trace_enable)
);
dkcm_controller dkcm_controller(
	.host_clk(host_clk),
	.host_addr(host_addr),
	.host_we(host_we),
	.select(dkcm_controller__select),
	.host_data(host_data),
	.dkcm_busy(dkcm_busy),
	.dkcm_bus(dkcm_bus)
);
fdbk_loop fdbk_loop(
	.fdbk_input(fdbk_input),
	.set_wave(set_wave),
	.dkcm_bus(dkcm_bus),
	.host_clk(host_clk),
	.feedback_enable(feedback_enable),
	.integrate_enable(integrate_enable),
	.feedforward_data(feedforward_data),
	.clk40(clk40),
	.dds_substitute(dds_substitute),
	.outsig40(outsig40)
);
afterdemux afterdemux(
	.clk40(clk40),
	.host_clk(host_clk),
	.mode_control(afterdemux__mode_control),
	.outsig40(outsig40),
	.DE(DE),
	.OCLK(OCLK),
	.OSEL(OSEL)
);
status status(
	.host_clk(host_clk),
	.host_re(host_re),
	.host_we(host_we),
	.host_data(host_data),
	.errors(status__errors),
	.status(status__status),
	.error_en(status__error_en),
	.clk40(clk40),
	.trace_enable(trace_enable),
	.dkcm_busy(dkcm_busy),
	.pll_muxout_(pll_muxout_),
	.trigger_skipped(trigger_skipped),
	.rf_on_sync(rf_on_sync),
	.sync_error(sync_error),
	.sync_missing(sync_missing),
	.clk40_missing_pulse(clk40_missing_pulse),
	.daov_(daov_),
	.dbov_(dbov_),
	.dcov_(dcov_),
	.ddov_(ddov_),
	.lrc_slot(lrc_slot),
	.il_stat_(il_stat_),
	.LED2(LED2)
);
stopwatch stopwatch(
	.host_clk(host_clk),
	.host_we(host_we),
	.control_sel(stopwatch__control_sel),
	.host_data(host_data),
	.host_addr(host_addr),
	.readout(stopwatch__readout),
	.clk40(clk40),
	.rf_on_sync(rf_on_sync)
);

// regwrite:
always @(posedge host_clk or posedge rst) if (rst) begin
	dds__set_i <= 0;
	dds__set_q <= 0;
	dds__freq <= 0;
	rf_timer__totalizer_delay <= 0;
	rf_timer__config_word <= 0;
	history2e__ustop_count <= 0;
	history2e__uhistory_config <= 0;
	history2e__dstop_count <= 0;
	history2e__dhistory_config <= 0;
	afterdemux__mode_control <= 0;
end else begin
	if (host_we & host_addr==14'b00000000100000) dds__set_i <= host_data;
	if (host_we & host_addr==14'b00000000100001) dds__set_q <= host_data;
	if (host_we & host_addr==14'b00000000100010) dds__freq <= host_data;
	if (host_we & host_addr==14'b00000000101000) rf_timer__totalizer_delay <= host_data;
	if (host_we & host_addr==14'b00000000100011) rf_timer__config_word <= host_data;
	if (host_we & host_addr==14'b00000000100100) history2e__ustop_count <= host_data;
	if (host_we & host_addr==14'b00000000100101) history2e__uhistory_config <= host_data;
	if (host_we & host_addr==14'b00000000100110) history2e__dstop_count <= host_data;
	if (host_we & host_addr==14'b00000000100111) history2e__dhistory_config <= host_data;
	if (host_we & host_addr==14'b00000000101001) afterdemux__mode_control <= host_data;
end

// selects:
assign           sport__hselect = (host_addr[13: 2]==12'b000000010101  );
assign       shadow_ram__select = (host_addr[13: 5]== 9'b000000001     );
assign      feedforward__select = (host_addr[13: 9]== 5'b00110         );
assign        rf_timer__hselect = (host_addr[13: 3]==11'b00000011000   );
assign  dkcm_controller__select = (host_addr[13: 3]==11'b00000000110   );
assign         status__error_en = (host_addr[13: 0]==14'b00000000010000);
assign   stopwatch__control_sel = (host_addr[13: 3]==11'b00000001100   );

// regread:
reg [15:0] host_read_pipe;
assign host_read = 0 |
	      feedforward__host_dout & {16{host_addr[13: 9]== 5'b00110         }} |
	         rf_timer__host_read & {16{host_addr[13: 3]==11'b00000011000   }} |
	      history2e__traced_dout & {16{host_addr[13: 9]== 5'b10000         }} |
	      history2e__trace1_dout & {16{host_addr[13: 9]== 5'b10100         }} |
	      history2e__trace2_dout & {16{host_addr[13: 9]== 5'b11000         }} |
	      history2e__trace3_dout & {16{host_addr[13: 9]== 5'b11100         }} |
	              host_read_pipe & {16{host_addr[13: 7]== 7'b0000000       }};
always @(posedge host_clk or posedge rst) if (rst) begin
	host_read_pipe <= 0;
end else begin
	host_read_pipe <= 0 |
	        config_rom__read_bus & {16{host_addr[13: 4]==10'b0000000000    }} |
	                sport__odata & {16{host_addr[13: 2]==12'b000000010101  }} |
	        shadow_ram__read_bus & {16{host_addr[13: 5]== 9'b000000001     }} |
	             totalizer__dout & {16{host_addr[13: 2]==12'b000000000111  }} |
	history2e__ucnt_at_pulse_end & {16{host_addr[13: 0]==14'b00000000010010}} |
	history2e__dcnt_at_pulse_end & {16{host_addr[13: 0]==14'b00000000010011}} |
	              status__errors & {16{host_addr[13: 0]==14'b00000000010000}} |
	              status__status & {16{host_addr[13: 0]==14'b00000000010001}} |
	          stopwatch__readout & {16{host_addr[13: 3]==11'b00000001100   }};
end

// 0 errors

endmodule

HierarchyFilesModulesSignalsTasksFunctionsHelp

This page: Maintained by: ldoolitt@recycle.lbl.gov
Created:Wed May 19 11:23:02 2004
From: llrf_mebt.v

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