// Verilog ramdp512x16 definition
// No copyright is claimed on this machine-generated code.
// Automatically generated from perl bram.pl 16 9
// bram.pl is written by Larry Doolittle <ldoolitt@recycle.lbl.gov>
// 512 x 16 dual port RAM, aggregated from
// 2 instances of 512 x 8 Virtex Block RAM
`timescale 1ns / 1ns
module ramdp512x16(
ADDRA, RSTA, ENA, WEA, CLKA, DIA, DOA,
ADDRB, RSTB, ENB, WEB, CLKB, DIB, DOB);
input [8:0] ADDRA;
input RSTA, ENA, WEA, CLKA;
input [15:0] DIA;
output [15:0] DOA;
input [8:0] ADDRB;
input RSTB, ENB, WEB, CLKB;
input [15:0] DIB;
output [15:0] DOB;
wire [8:0] ADDRA;
wire RSTA, ENA, WEA, CLKA;
wire [15:0] DIA;
wire [15:0] DOA;
wire [8:0] ADDRB;
wire RSTB, ENB, WEB, CLKB;
wire [15:0] DIB;
wire [15:0] DOB;
RAMB4_S8_S8 b0(
.ADDRA (ADDRA),
.RSTA (RSTA),
.ENA (ENA),
.WEA (WEA),
.CLKA (CLKA),
.DIA (DIA[7:0]),
.DOA (DOA[7:0]),
.ADDRB (ADDRB),
.RSTB (RSTB),
.ENB (ENB),
.WEB (WEB),
.CLKB (CLKB),
.DIB (DIB[7:0]),
.DOB (DOB[7:0])
);
RAMB4_S8_S8 b1(
.ADDRA (ADDRA),
.RSTA (RSTA),
.ENA (ENA),
.WEA (WEA),
.CLKA (CLKA),
.DIA (DIA[15:8]),
.DOA (DOA[15:8]),
.ADDRB (ADDRB),
.RSTB (RSTB),
.ENB (ENB),
.WEB (WEB),
.CLKB (CLKB),
.DIB (DIB[15:8]),
.DOB (DOB[15:8])
);
endmodule