// Verilog srl16x4e definition
// No copyright is claimed on this machine-generated code.
// Automatically generated from perl srle.pl 4
// srle.pl is written by Larry Doolittle <ldoolitt@recycle.lbl.gov>

// 16 x 4 shift register, aggregated from
// 4 instances of 16 x 1 Virtex SRL16E shift registers

`timescale 1ns / 1ns


module srl16x4e(Q, A0, A1, A2, A3, CE, CLK, D);
        input A0, A1, A2, A3, CE, CLK;
        input  [3:0] D;
        output [3:0] Q;
        wire   [3:0] Q, D;
	SRL16E d0(.Q(Q[0]), .A0(A0), .A1(A1), .A2(A2), .A3(A3),
		.CE(CE), .CLK(CLK), .D(D[0]));
	SRL16E d1(.Q(Q[1]), .A0(A0), .A1(A1), .A2(A2), .A3(A3),
		.CE(CE), .CLK(CLK), .D(D[1]));
	SRL16E d2(.Q(Q[2]), .A0(A0), .A1(A1), .A2(A2), .A3(A3),
		.CE(CE), .CLK(CLK), .D(D[2]));
	SRL16E d3(.Q(Q[3]), .A0(A0), .A1(A1), .A2(A2), .A3(A3),
		.CE(CE), .CLK(CLK), .D(D[3]));

endmodule