The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design enhapll_32_77.v. The design enhapll_32_77.v has Stratix AUTO pll configured in NO_COMPENSATION mode The primary clock input to the PLL is INCLK0, with clock period 25000 ps. CLK0 multiply by = 32, CLK0 divide by = 77, CLK0 phase_shift = 0 Output port LOCKED is used. This port will go high when the PLL locks to the input clock. Input port ARESET is used. This port is active high. When asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted.