diff -ur Verilog/FPGA_modules/codec_control.v gang-verilog/FPGA_modules/codec_control.v
--- Verilog/FPGA_modules/codec_control.v	2006-10-27 12:43:58.000000000 -0700
+++ gang-verilog/FPGA_modules/codec_control.v	2007-04-11 15:08:04.000000000 -0700
@@ -17,7 +17,7 @@
 	output reg rst,
 	
 	output reg [23:0] out_l, out_r,
-	output adc_dav_l, adc_dav_r,
+	output reg adc_dav_l, adc_dav_r,
 	
 	input [31:0] fir_out_r, fir_out_l,
 	
@@ -83,7 +83,8 @@
 reg [23:0] new_word;
 
 wire l_dav, r_dav;
-reg l_dav_req, r_dav_req, adc_dav_l, adc_dav_r, adc_dav_l_int, adc_dav_r_int;
+// reg adc_dav_l, adc_dav_r;
+reg l_dav_req, r_dav_req, adc_dav_l_int, adc_dav_r_int;
 wire [23:0] adc_out_l, adc_out_r;
 
 wire wr_spi;
diff -ur Verilog/FPGA_modules/cordic_ampl_phy.v gang-verilog/FPGA_modules/cordic_ampl_phy.v
--- Verilog/FPGA_modules/cordic_ampl_phy.v	2006-07-25 08:33:10.000000000 -0700
+++ gang-verilog/FPGA_modules/cordic_ampl_phy.v	2007-04-11 15:17:08.000000000 -0700
@@ -103,10 +103,14 @@
 
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || counter==6'd36) begin 
+	if (~clrn) begin
 		counter	<= # dly 6'd0;
-	end else if (start || |counter) begin
-		counter	<= # dly counter + 1'b1;
+	end else begin
+	    if (counter==6'd36) begin 
+			counter	<= # dly 6'd0;
+		end else if (start || |counter) begin
+			counter	<= # dly counter + 1'b1;
+		end
 	end   
 end
 
diff -ur Verilog/FPGA_modules/cordic_windower.v gang-verilog/FPGA_modules/cordic_windower.v
--- Verilog/FPGA_modules/cordic_windower.v	2006-09-13 15:55:54.000000000 -0700
+++ gang-verilog/FPGA_modules/cordic_windower.v	2007-04-12 12:17:52.000000000 -0700
@@ -53,7 +53,9 @@
 
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || ~en_windowing) begin
+	if (~clrn) begin
+		waiting_first_dav	<= # dly 1'b1;	
+	end else if ( ~en_windowing) begin
 		waiting_first_dav	<= # dly 1'b1;
 	end else if (dav_in_l||dav_in_r) begin
 		waiting_first_dav	<= # dly ~waiting_first_dav;  
@@ -61,7 +63,9 @@
 end
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || ~en_windowing) begin
+	if (~clrn) begin
+		first_sample_received	<= # dly 1'b0;	
+	end else if ( ~en_windowing) begin
 		first_sample_received	<= # dly 1'b0;
 	end else if (~waiting_first_dav) begin
 		first_sample_received	<= # dly 1'b1;  
@@ -69,7 +73,9 @@
 end
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || ~en_windowing) begin
+	if (~clrn) begin 
+		mult_coef	<= # dly 36'h0;			
+	end else if (~en_windowing) begin
 		mult_coef	<= # dly 36'h0;		
 	end else if (waiting_first_dav && first_sample_received && win_calc_done) begin	
 		mult_coef	<= # dly win_calc_out[35:0];
@@ -155,7 +161,10 @@
 end
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || ~en_windowing) begin
+	if (~clrn) begin
+		phase			<= # dly 19'h0;
+		win_calc_start	<= # dly 1'b0;
+	end else if (~en_windowing) begin
 		phase			<= # dly 19'h0;
 		win_calc_start	<= # dly 1'b0;
 	end else if (waiting_first_dav && (dav_in_l||dav_in_r)) begin	
diff -ur Verilog/FPGA_modules/cs4272_dacs.v gang-verilog/FPGA_modules/cs4272_dacs.v
--- Verilog/FPGA_modules/cs4272_dacs.v	2006-04-20 09:30:34.000000000 -0700
+++ gang-verilog/FPGA_modules/cs4272_dacs.v	2007-04-12 12:11:10.000000000 -0700
@@ -18,10 +18,14 @@
 end
 
 always @(posedge sclk or negedge clrn) begin
-	if (~clrn || old_lrck^lrck) begin
+	if (~clrn) begin
 		sh_count	<= # dly 5'h0;
 	end else begin
-		sh_count	<= # dly sh_count + 1'b1;
+		if(old_lrck^lrck) begin
+			sh_count	<= # dly 5'h0;
+		end else begin
+			sh_count	<= # dly sh_count + 1'b1;
+		end
 	end
 end
 			 		
diff -ur Verilog/FPGA_modules/fft_mem_master.v gang-verilog/FPGA_modules/fft_mem_master.v
--- Verilog/FPGA_modules/fft_mem_master.v	2006-09-14 09:32:40.000000000 -0700
+++ gang-verilog/FPGA_modules/fft_mem_master.v	2007-04-12 12:34:28.000000000 -0700
@@ -207,7 +207,9 @@
 //REGISTERS
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || ~acquiring) begin
+	if (~clrn) begin
+		first_fir_dec_dav	<= # dly 1'b0;	
+	end else if (~acquiring) begin
 		first_fir_dec_dav	<= # dly 1'b0;
 	end else begin
 		if (fir_dec_dav_l || fir_dec_dav_r) begin
@@ -255,7 +257,9 @@
 
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin 
+		trig_number	<= # dly 32'h0;	
+	end else if (command==command_clear_all) begin
 		trig_number	<= # dly 32'h0;
 	end else if (trigger) begin
 		trig_number	<= # dly trig_number + 1'b1;
@@ -263,7 +267,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn ) begin
+		fir_dec_dav_counter	<= # dly 1'b0;	
+	end else if (command==command_clear_all) begin
 		fir_dec_dav_counter	<= # dly 1'b0;
 	end else if (fir_dec_dav) begin
 		fir_dec_dav_counter	<= # dly fir_dec_dav_counter + 1'b1;
@@ -273,7 +279,9 @@
 // CONFIGURATION BITS
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		mode_normal	<= # dly 1'b0;	
+	end else if (command==command_clear_all) begin
 		mode_normal	<= # dly 1'b0;
 	end else if (command==command_normal_mode) begin
 		mode_normal	<= # dly 1'b1;
@@ -283,7 +291,9 @@
 end
 	
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		trigger_armed	<= # dly 1'b0;	
+	end else if	( command==command_clear_all) begin
 		trigger_armed	<= # dly 1'b0;
 	end else if (mode_normal || command==command_arm_trigger) begin
 		trigger_armed	<= # dly 1'b1;
@@ -293,7 +303,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin 
+		raw_data_required	<= # dly 1'b1;	
+	end else if ( command==command_clear_all) begin
 		raw_data_required	<= # dly 1'b1;
 	end else if (command==command_fft_mode) begin
 		raw_data_required	<= # dly 1'b0;
@@ -303,7 +315,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		fft_data_required	<= # dly 1'b1;	
+	end else if ( command==command_clear_all) begin
 		fft_data_required	<= # dly 1'b1;
 	end else if (command==command_raw_mode) begin
 		fft_data_required	<= # dly 1'b0;
@@ -314,7 +328,9 @@
 
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		window_req	<= # dly 1'b0;
+	end else if (command==command_clear_all) begin
 		window_req	<= # dly 1'b0;
 	end else if (command==command_dis_windowing) begin
 		window_req	<= # dly 1'b0;
@@ -324,7 +340,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		pll_fft_mode	<= # dly 1'b0;	
+	end else if ( command==command_clear_all) begin
 		pll_fft_mode	<= # dly 1'b0;
 	end else if (command==command_pll_fft_mode_off) begin
 		pll_fft_mode	<= # dly 1'b0;
@@ -334,7 +352,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin 
+		fft_lenght	<= # dly 4'h4; //1024 points	
+	end else if (command==command_clear_all) begin
 		fft_lenght	<= # dly 4'h4; //1024 points
 	end else if (command==command_set_fft_lenght) begin
 		fft_lenght	<= # dly command_reg[3:0];
@@ -342,7 +362,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || command==command_clear_all) begin
+	if (~clrn) begin
+		pre_acq_lenght	<= # dly 5'h0; //256k points :the real acq_lenght is fixed by the fft lenght	
+	end else if (command==command_clear_all) begin
 		pre_acq_lenght	<= # dly 5'h0; //256k points :the real acq_lenght is fixed by the fft lenght
 	end else if (command==command_set_acq_lenght) begin
 		pre_acq_lenght	<= # dly command_reg[4:0];
@@ -360,7 +382,9 @@
 //FIR&DECIMATOR OVERFLOW DURING ACQUISITION REGISTERS
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || (trigger_armed && trigger_acq)) begin
+	if (~clrn) begin 
+		fir_dec_ovf_l_reg	<= # dly 1'b0;	
+	end else if ( (trigger_armed && trigger_acq)) begin
 		fir_dec_ovf_l_reg	<= # dly 1'b0;
 	end else if (acquiring && fir_dec_ovf_l) begin
 			fir_dec_ovf_l_reg	<= # dly 1'b1;
@@ -368,7 +392,9 @@
 end
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn || (trigger_armed && trigger_acq)) begin
+	if (~clrn) begin 
+		fir_dec_ovf_r_reg	<= # dly 1'b0;	
+	end else if  ((trigger_armed && trigger_acq)) begin
 		fir_dec_ovf_r_reg	<= # dly 1'b0;
 	end else if (acquiring && fir_dec_ovf_r) begin
 		fir_dec_ovf_r_reg	<= # dly 1'b1;
@@ -380,7 +406,9 @@
 assign fft_x_t	= sram_data_synch;
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || acquiring) begin
+	if (~clrn) begin
+		fft_overflow_reg	<= # dly 1'b0;	
+	end else if (acquiring) begin
 		fft_overflow_reg	<= # dly 1'b0;
 	end else if ((state==s_fft_rd || state==s_fft_wr)&& fft_overflow) begin
 		fft_overflow_reg	<= # dly 1'b1;
@@ -447,7 +475,32 @@
 
 
 always @(posedge clk or negedge clrn)begin
-	if (~clrn ||  command==command_clear_all) begin
+	if (~clrn) begin 
+		state			<= # dly s_idle;
+		sram_data_int	<= # dly 32'h0;
+		oe_data_int		<= # dly 1'b0;
+		sram_addr		<= # dly 21'b0;
+		sram_oe_n		<= # dly 1'b1;
+		sram_gwe_n		<= # dly 1'b1;
+		vme_dout_dav_mem<= # dly 1'b0;	
+		counter			<= # dly 5'h0;
+		adc_l_wr_req	<= # dly 1'b0;
+		adc_r_wr_req	<= # dly 1'b0;
+		acquiring		<= # dly 1'b0;
+		raw_data_read	<= # dly 1'b1;
+		fft_data_read	<= # dly 1'b1;
+		mem_pointer		<= # dly 18'h0;
+		time_stamp		<= # dly 32'h0;
+		fft_start		<= # dly 1'b0;
+		fft_iteration	<= # dly 4'b0;
+		fft_n_2			<= # dly 16'h0;
+		sram_addr_inc	<= # dly 18'd256;	
+		fft_mod_req		<= # dly 1'b0;
+		int_for_raw		<= # dly 1'b0;
+		int_for_fft		<= # dly 1'b0;
+		last_read_addr	<= # dly 21'h0;
+	
+	end else if ( command==command_clear_all) begin
 		state			<= # dly s_idle;
 		sram_data_int	<= # dly 32'h0;
 		oe_data_int		<= # dly 1'b0;
diff -ur Verilog/FPGA_modules/q_pll.v gang-verilog/FPGA_modules/q_pll.v
--- Verilog/FPGA_modules/q_pll.v	2006-11-14 16:22:36.000000000 -0800
+++ gang-verilog/FPGA_modules/q_pll.v	2007-04-11 15:15:48.000000000 -0700
@@ -468,10 +468,14 @@
 //**********************************************
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || disable_w_pll_mod) begin
+	if (~clrn) begin
 		wpll_mod_ampl	<= # dly 32'h0000_0000;
-	end else if (vme_reg_space_cs && vme_wr && vme_addr[4:0]==addr_wpll_mod_ampl) begin
-		wpll_mod_ampl	<= # dly vme_din;
+	end else begin
+	    if (disable_w_pll_mod) begin
+		    wpll_mod_ampl	<= # dly 32'h0000_0000;
+	    end else if (vme_reg_space_cs && vme_wr && vme_addr[4:0]==addr_wpll_mod_ampl) begin
+		    wpll_mod_ampl	<= # dly vme_din;
+		end
 	end
 end
 
@@ -505,10 +509,14 @@
 //**********************************************
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || disable_se) begin
-		se12_ampl	<= # dly 32'h0000_0000;
-	end else if (vme_reg_space_cs && vme_wr && vme_addr[4:0]==addr_se12_ampl) begin
-		se12_ampl	<= # dly vme_din;
+	if (~clrn) begin
+     	se12_ampl	<= # dly 32'h0000_0000;
+	end else begin
+	    if (disable_se) begin
+		    se12_ampl	<= # dly 32'h0000_0000;
+	    end else if (vme_reg_space_cs && vme_wr && vme_addr[4:0]==addr_se12_ampl) begin
+		    se12_ampl	<= # dly vme_din;
+		end
 	end
 end
 
diff -ur Verilog/FPGA_modules/trigger_manager.v gang-verilog/FPGA_modules/trigger_manager.v
--- Verilog/FPGA_modules/trigger_manager.v	2006-09-26 09:42:44.000000000 -0700
+++ gang-verilog/FPGA_modules/trigger_manager.v	2007-04-12 12:16:24.000000000 -0700
@@ -138,7 +138,11 @@
 end				
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || (cs && wr) || (hw_trig_delay_counter==hw_trig_delay)) begin
+	if (~clrn) begin
+		hw_trig_delay_counter	<= # dly 24'h0;	
+	end else if (cs && wr) begin
+		hw_trig_delay_counter	<= # dly 24'h0;	
+	end else if (hw_trig_delay_counter==hw_trig_delay) begin
 		hw_trig_delay_counter	<= # dly 24'h0;
 	end else if ((hw_trig_delay_counter==24'h0) && (hw_trig_armed&&hw_trigger_pulse)) begin
 		hw_trig_delay_counter	<= # dly hw_trig_delay_counter + 1'b1;
@@ -200,7 +204,11 @@
 end
 	
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || (cs && wr) || ~tick_enabled) begin
+	if (~clrn) begin
+		counter_acq	<= # dly 18'h0;	
+	end else if (cs && wr) begin
+		counter_acq	<= # dly 18'h0;	
+	end else if (~tick_enabled) begin
 		counter_acq	<= # dly 18'h0;
 	end else if (tick_enabled && ~tick_enabled_old) begin
 		counter_acq <= # dly tick2skip_acq;
@@ -210,7 +218,11 @@
 end
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn || (cs && wr) || ~tick_enabled) begin
+	if (~clrn) begin
+		counter_chirp	<= # dly 18'h0;
+	end else if (cs && wr) begin
+		counter_chirp	<= # dly 18'h0;
+	end else if (~tick_enabled) begin
 		counter_chirp	<= # dly 18'h0;
 	end else if (tick_enabled && ~tick_enabled_old) begin
 		counter_chirp <= # dly tick2skip_chirp;		
@@ -220,7 +232,10 @@
 end
 
 always @(posedge clk or negedge clrn) begin
-	if (~clrn ||(command==command_tick_enable)) begin
+	if (~clrn) begin
+		start_acq		<= # dly 1'b0;
+		active_channel	<= # dly 1'b0;
+	end else if(command==command_tick_enable) begin
 		start_acq		<= # dly 1'b0;
 		active_channel	<= # dly 1'b0;
 	end else begin