Spartan3 FT256 layout
Rendition of routing for a Xilinx Spartan-3 FT256, done
with a patched-up version of
pcb,
based on the 20040903 snapshot.
Layer stackup:
- Component/routing
- Ground
- Power
- Routing
- Ground
- Solder/routing
Layers 1 and 2:
Layer 3:
Layers 4 and 6:
Details
- Original layout file for pcb.
- 5 mil routing traces, 8 mil dumbbell traces, 20 mil power traces
- 22 mil via pads, 12 mil hole
- 15.75 mil BGA pads, 1 mm = 39.37 mil BGA pad pitch
- Space between traces and via pads is (39.37 - 22 - 5)/2 = 6.185 mil
- Space between traces and BGA pads is (39.37 - 15.75 - 5)/2 = 9.31 mil
- 0603 decoupling caps
Good points:
- All 184 non-power pins routed out (on three layers, 100+60+24)
- Compact design, no wasted layers
- BGA pad placement on a precise 1.00 mm grid
- Routing points all lie on a precise 0.50 mm grid
- One decoupling cap per VCCINT and VCCAUX pad
- Good low impedance power plane connections to each VCCO and VCCAUX pad
- Passes DRC with 5 mil line, 6 mil space
Bad points:
- No attention paid to keeping differential pairs together
- Only one decoupling cap per VCCO pad triplet
- My indecision on voltage assignments to VCCO makes for a chopped-up power plane; presumably that effect will disappear in a real design
Compared to previous postings, this version:
- Uses a more realistic footprint for the 0603 caps (pcb newlib file, see
discussion on geda-users
mailing list, subject "pcb SMT footprints")
- Uses fatter power traces (thanks, Hal2000, for encouragement)
- Orients all capacitors with pad 2 at ground
- More tuning of my patches to pcb-20040903
Comparison to DSPCARD
Darrell Harmon's DSPCARD is also laid
out using pcb, and incorporates a Spartan3-FT256.
| layout | LRD | DH |
| layers | 6 | 4 |
| routed signals | 184 | 131 |
| capacitor size | 0603 | 0402 |
| VCCO caps | 8 | 8 |
| VCCAUX caps | 8 | 8 |
| VCCINT caps | 8 | 4 |
| lines | 5 mil | 6 mil |
| BGA pads | 15.75 mil | 13.39 mil |
| Via hole | 12 mil | 15 mil |
| Via pad | 22 mil | 30 mil |
| Pad-trace-pad clearance | 9.3 mil | 10 mil |
| Via-trace-via clearance | 6.2 mil | not used |
| status | incomplete | tested |
Darrell adds: "... the sizes I used were not ideal, but were to allow for the
lowest cost prototype. The final board will use smaller vias and 0.4 mm
BGA pads as recommended by Xilinx."
Reference
- Discussion on geda-users mailing list, subject "Spartan3 FT256 layout in PCB"
Created November 11, 2005
Updated December 5, 2005
Larry Doolittle