# Synthesizable Verilog for LBNL LLRF system
# Please read the README file.
# See the test directory for, umm, tests.

MACHINE_GENERATED_VERILOG = ramdp512x16.v ramdp1024x12.v ramdp1024x32.v ramdp4096x12.v \
     srl16x12e.v srl16x16e.v srl16x19e.v srl16x24e.v \
     adctest_p.v history_p.v dds_p.v

all: $(MACHINE_GENERATED_VERILOG)

# useful stuff:
ramdp512x16.v: bram.pl
	perl $< 16 9 >$@

ramdp1024x12.v: bram.pl
	perl $< 12 10 >$@

ramdp1024x32.v: bram.pl
	perl $< 32 10 >$@

ramdp4096x12.v: bram.pl
	perl $< 12 12 >$@

ramdp2048x14.v: bram.pl
	perl $< 14 11 >$@

srl16x12e.v: srle.pl
	perl $< 12 >$@

srl16x14e.v: srle.pl
	perl $< 14 >$@

srl16x16e.v: srle.pl
	perl $< 16 >$@

srl16x19e.v: srle.pl
	perl $< 19 >$@

srl16x24e.v: srle.pl
	perl $< 24 >$@

# generate preprocessed versions of Verilog programs
%_p.v: %.v
	iverilog -E -o $@ $<

# just for fun:
LOC: loc
	sh $<

# wishful thinking, maybe Icarus 0.8 will handle this:
adctest.edif: adctest.v fdbk_loop.v error3.v kcm.v afterburner.v \
         ds2401.v sportx.v timing.v flasher.v \
         ramdp1024x12.v ramdp1024x32.v ramdp4096x12.v
	iverilog -Wall -tfpga -parch=virtex -o $@ $^ 

clean:
	rm -f $(MACHINE_GENERATED_VERILOG) adctest.edif