# LLRF Constraints file
# pin numbering applies to Xilinx XC2Sxxx-xPQ208 chips
NET CLK LOC=P77;
NET P_Down LOC=P83;
NET DA<0> LOC=P3;
NET DA<1> LOC=P4;
NET DA<2> LOC=P5;
NET DA<3> LOC=P6;
NET DA<4> LOC=P7;
NET DA<5> LOC=P8;
NET DA<6> LOC=P9;
NET DA<7> LOC=P10;
NET DA<8> LOC=P14;
NET DA<9> LOC=P15;
NET DA<10> LOC=P16;
NET DA<11> LOC=P17;
NET DAOV LOC=P18;
NET DB<0> LOC=P20;
NET DB<1> LOC=P21;
NET DB<2> LOC=P22;
NET DB<3> LOC=P23;
NET DB<4> LOC=P24;
NET DB<5> LOC=P29;
NET DB<6> LOC=P30;
NET DB<7> LOC=P31;
NET DB<8> LOC=P33;
NET DB<9> LOC=P34;
NET DB<10> LOC=P35;
NET DB<11> LOC=P36;
NET DBOV LOC=P37;
NET DC<0> LOC=P41;
NET DC<1> LOC=P42;
NET DC<2> LOC=P43;
NET DC<3> LOC=P44;
NET DC<4> LOC=P45;
NET DC<5> LOC=P46;
NET DC<6> LOC=P47;
NET DC<7> LOC=P48;
NET DC<8> LOC=P49;
NET DC<9> LOC=P57;
NET DC<10> LOC=P58;
NET DC<11> LOC=P59;
NET DCOV LOC=P60;
NET DD<0> LOC=P61;
NET DD<1> LOC=P62;
NET DD<2> LOC=P63;
NET DD<3> LOC=P67;
NET DD<4> LOC=P68;
NET DD<5> LOC=P69;
NET DD<6> LOC=P70;
NET DD<7> LOC=P71;
NET DD<8> LOC=P73;
NET DD<9> LOC=P74;
NET DD<10> LOC=P75;
NET DD<11> LOC=P81;
NET DDOV LOC=P82;

NET SLEEP LOC=P87;
NET DE<0> LOC=P88;
NET DE<1> LOC=P89;
NET DE<2> LOC=P90;
NET DE<3> LOC=P94;
NET DE<4> LOC=P95;
NET DE<5> LOC=P96;
NET DE<6> LOC=P97;
NET DE<7> LOC=P98;
NET DE<8> LOC=P99;
NET DE<9> LOC=P100;
NET DE<10> LOC=P101;
NET DE<11> LOC=P102;

NET CLK80X LOC=P80;

NET PD<0> LOC=P120;
NET PD<1> LOC=P121;
NET PD<2> LOC=P122;
NET PD<3> LOC=P123;
NET PD<4> LOC=P125;
NET PD<5> LOC=P126;
NET PD<6> LOC=P127;
NET PD<7> LOC=P129;
NET PD<8> LOC=P132;
NET PD<9> LOC=P133;
NET PD<10> LOC=P134;
NET PD<11> LOC=P135;
NET PD<12> LOC=P136;
NET PD<13> LOC=P138;
NET PD<14> LOC=P139;
NET PD<15> LOC=P140;

NET CK_host    LOC=P152;  # PC0
NET ALE_host   LOC=P162;  # PC1
NET RD_host    LOC=P163;  # PC2
NET WE_host    LOC=P164;  # PC3
NET RDY_host   LOC=P165;  # PC4
NET CS0_host   LOC=P166;  # PC5
NET INT_host   LOC=P168;  # PC7

NET PLL_LE     LOC=P189;  # P1  DG0
NET PLL_DATA   LOC=P191;  # P2  DG1
NET PLL_CLK    LOC=P192;  # P3  DG2
NET PLL_CE     LOC=P193;  # P4  DG3
NET PLL_MUXOUT LOC=P188;  # P5  DG4

NET RF_ON      LOC=P173;  # Trigger   DF00  FPGA reads LOW when external gate is active
NET RF_KILL    LOC=P174;  # RF_enable DF01  FPGA sets this LOW to ALLOW rf
NET IL_STAT    LOC=P175;  # Status    DF02  FPGA reads LOW when interlocks (and RF_enable) ALLOW rf
NET SCLK       LOC=P179;  # H1  DF03  MAX1202, TCN75, MAX5742
# NET SDIN     LOC=P178;  # H2 (SHORTED)    DF04 FPGA output to MAX1202, MAX5742
NET SDIN       LOC=P172;  # H2 (substitute) DF04 FPGA output to MAX1202, MAX5742
NET DOUT1202   LOC=P181;  # H3  DF05  driven by MAX1202
NET SDA75      LOC=P176;  # H4  DF06  I/O with TCN75
NET CS1202     LOC=P180;  # H5  DF07  Chip Select for MAX1202
NET CS5742     LOC=P187;  # H6  DF08  Chip Select for MAX5742
NET DS2401     LOC=P194;  # H7  DF09  I/O with DS2401

#   LED1 comes directly from nanoEngine
NET LED2 LOC=P205;  # J7-11  DU7
NET LED3 LOC=P204;  # J7-12  DU6
NET LED4 LOC=P203;  # J7-14  DU5
NET DIO1 LOC=P202;  # J7-15  DU4
NET DIO2 LOC=P201;  # J7-16  DU3
NET DIO3 LOC=P200;  # J7-18  DU2
NET DIO4 LOC=P199;  # J7-19  DU1
#   DIO5 comes directly from nanoEngine
NET DIO6 LOC=P195;  # J7-22  DU0

# Constraints for Foundation 4.2i
# Over-specify the clocks a little
NET CLK period=19;        # 6 ns slack
NET CK_host period=30;    # 10 ns slack
NET CLK80X period=10;     # 2.5 ns slack