//cordic processor //14 bit input for x, y and phase // (but because of rounding errors, the output is really only accurate to about 11 bits) // needs implementation of the highest order bit (pi) // still could use some language cleanup // can probably shave some cells since: // we only want xout, not yout, so we can drop some low-order bits of y // as z gets smaller, we don't need to continue with as many high order bits module adder13(a,b,sum,control); input [13:0] a,b; input control; output [13:0] sum; assign sum = control ? (a + b) : (a - b); endmodule module adder12(a,b,sum,control); input [13:0] a; input[12:0] b; input control; output [13:0] sum; assign sum = control ? (a + b) : (a - b); endmodule module adder11(a,b,sum,control); input [13:0] a; input[11:0] b; input control; output [13:0] sum; assign sum = {a[13], {control ? (a[12:0] + b) : (a[12:0] - b)}}; endmodule module adder10(a,b,sum,control); input [13:0] a; input[10:0] b; input control; output [13:0] sum; assign sum = {a [13:12], {control ? (a[11:0] + b) : (a[11:0] - b)}}; endmodule module adder9(a,b,sum,control); input [13:0] a; input[9:0] b; input control; output [13:0] sum; assign sum = {a[13:11], {control ? (a[10:0] + b) : (a[10:0] - b)}}; endmodule module adder8(a,b,sum,control); input [13:0] a; input[8:0] b; input control; output [13:0] sum; assign sum = {a[13:10], {control ? (a[9:0] + b) : (a[9:0] - b)}}; endmodule module adder7(a,b,sum,control); input [13:0] a; input[7:0] b; input control; output [13:0] sum; assign sum = {a[13:9], {control ? (a[8:0] + b) : (a[8:0] - b)}}; endmodule module adder6(a,b,sum,control); input [13:0] a; input[6:0] b; input control; output [13:0] sum; assign sum = {a[13:8], {control ? (a[7:0] + b) : (a[7:0] - b)}}; endmodule module adder5(a,b,sum,control); input [13:0] a; input[5:0] b; input control; output [13:0] sum; assign sum = {a[13:7], {control ? (a[6:0] + b) : (a[6:0] - b)}}; endmodule module adder4(a,b,sum,control); input [13:0] a; input[4:0] b; input control; output [13:0] sum; assign sum = {a[13:6], {control ? (a[5:0] + b) : (a[5:0] - b)}}; endmodule module adder3(a,b,sum,control); input [13:0] a; input[3:0] b; input control; output [13:0] sum; assign sum = {a[13:5], {control ? (a[4:0] + b) : (a[4:0] - b)}}; endmodule module adder2(a,b,sum,control); input [13:0] a; input[2:0] b; input control; output [13:0] sum; assign sum = {a[13:4], {control ? (a[3:0] + b) : (a[3:0] - b)}}; endmodule module cordic(clk, xin, yin, phasein, xout, yout, phaseout); input clk; input [13:0] xin, yin, phasein; output[13:0] xout, yout, phaseout; wire [13:0] xout, yout, phaseout; wire [13:0] xw0; wire [13:0] xw1; wire [13:0] xw2; wire [13:0] xw3; wire [13:0] xw4; wire [13:0] xw5; wire [13:0] xw6; wire [13:0] xw7; wire [13:0] xw8; wire [13:0] xw9; wire [13:0] xw10; wire [13:0] xw11; wire [13:0] xw12; reg [13:0] x0; reg [12:0] x1; reg [11:0] x2; reg [10:0] x3; reg [9:0] x4; reg [8:0] x5; reg [7:0] x6; reg [6:0] x7; reg [5:0] x8; reg [4:0] x9; reg [3:0] x10; reg [2:0] x11; reg [1:0] x12; wire [13:0] yw0; wire [13:0] yw1; wire [13:0] yw2; wire [13:0] yw3; wire [13:0] yw4; wire [13:0] yw5; wire [13:0] yw6; wire [13:0] yw7; wire [13:0] yw8; wire [13:0] yw9; wire [13:0] yw10; wire [13:0] yw11; wire [13:0] yw12; reg [13:0] y0; reg [12:0] y1; reg [11:0] y2; reg [10:0] y3; reg [9:0] y4; reg [8:0] y5; reg [7:0] y6; reg [6:0] y7; reg [5:0] y8; reg [4:0] y9; reg [3:0] y10; reg [2:0] y11; reg [1:0] y12; wire [13:0] zw0; wire [13:0] zw1; wire [13:0] zw2; wire [13:0] zw3; wire [13:0] zw4; wire [13:0] zw5; wire [13:0] zw6; wire [13:0] zw7; wire [13:0] zw8; wire [13:0] zw9; wire [13:0] zw10; wire [13:0] zw11; wire [13:0] zw12; reg [13:0] z0; reg [13:0] z1; reg [13:0] z2; reg [13:0] z3; reg [13:0] z4; reg [13:0] z5; reg [13:0] z6; reg [13:0] z7; reg [13:0] z8; reg [13:0] z9; reg [13:0] z10; reg [13:0] z11; reg [13:0] z12; // signed 12-bit input angle [-2048 , 2047 ] represents the range [ -pi/2 , pi/2 ) // atan((0.5).^[0:12]')/(2*pi)*8192*4 // keep one high order 0 bit so these are valid signed numbers wire [13:0] a0 = 4096; // pi/4 wire [13:0] a1 = 2418; wire [13:0] a2 = 1277; wire [13:0] a3 = 648; wire [13:0] a4 = 326; wire [13:0] a5 = 163; wire [13:0] a6 = 81; wire [13:0] a7 = 41; wire [13:0] a8 = 20; wire [13:0] a9 = 10; wire [13:0] a10 = 5; wire [13:0] a11 = 3; assign xout = x12; assign yout = y12; assign phaseout = z12; adder13 ax1 (xw0, y0, xw1, z0[13]); adder13 ay1 (yw0, x0, yw1, ~z0[13]); adder13 az1 (z0, a0, zw1, z0[13]); adder12 ax2 (xw1, y1, xw2, z1[13]); adder12 ay2 (yw1, x1, yw2, ~z1[13]); adder13 az2 (z1, a1, zw2, z1[13]); adder11 ax3 (xw2, y2, xw3, z2[13]); adder11 ay3 (yw2, x2, yw3, ~z2[13]); adder13 az3 (z2, a2, zw3, z2[13]); adder10 ax4 (xw3, y3, xw4, z3[13]); adder10 ay4 (yw3, x3, yw4, ~z3[13]); adder13 az4 (z3, a3, zw4, z3[13]); adder9 ax5 (xw4, y4, xw5, z4[13]); adder9 ay5 (yw4, x4, yw5, ~z4[13]); adder13 az5 (z4, a4, zw5, z4[13]); adder8 ax6 (xw5, y5, xw6, z5[13]); adder8 ay6 (yw5, x5, yw6, ~z5[13]); adder13 az6 (z5, a5, zw6, z5[13]); adder7 ax7 (xw6, y6, xw7, z6[13]); adder7 ay7 (yw6, x6, yw7, ~z6[13]); adder13 az7 (z6, a6, zw7, z6[13]); adder6 ax8 (xw7, y7, xw8, z7[13]); adder6 ay8 (yw7, x7, yw8, ~z7[13]); adder13 az8 (z7, a7, zw8, z7[13]); adder5 ax9 (xw8, y8, xw9, z8[13]); adder5 ay9 (yw8, x8, yw9, ~z8[13]); adder13 az9 (z8, a8, zw9, z8[13]); adder4 ax10(xw9, y9, xw10, z9[13]); adder4 ay10(yw9, x9, yw10, ~z9[13]); adder13 az10(z9, a9, zw10, z9 [13]); adder3 ax11(xw10, y10, xw11, z10[13]); adder3 ay11(yw10, x10, yw11, ~z10[13]); adder13 az11(z10, a10, zw11, z10[13]); adder2 ax12(xw11, y11, xw12, z11[13]); adder2 ay12(yw11, x11, yw12, ~z11[13]); adder13 az12(z11, a11, zw12, z11[13]); always @ (posedge clk) begin x0 <= xin; y0 <= yin; z0 <= phasein; x1 <= xw1[13:1]; y1 <= yw1[13:1]; z1 <= zw1; x2 <= xw2[13:2]; y2 <= yw2[13:2]; z2 <= zw2; x3 <= xw3[13:3]; y3 <= yw3[13:3]; z3 <= zw3; x4 <= xw4[13:4]; y4 <= yw4[13:4]; z4 <= zw4; x5 <= xw5[13:5]; y5 <= yw5[13:5]; z5 <= zw5; x6 <= xw6[13:6]; y6 <= yw6[13:6]; z6 <= zw6; x7 <= xw7[13:7]; y7 <= yw7[13:7]; z7 <= zw7; x8 <= xw8[13:8]; y8 <= yw8[13:8]; z8 <= zw8; x9 <= xw9[13:9]; y9 <= yw9[13:9]; z9 <= zw9; x10 <= xw10[13:10]; y10 <= yw10[13:10]; z10 <= zw10; x11 <= xw11[13:11]; y11 <= yw11[13:11]; z11 <= zw11; x12 <= xw12[13:12]; y12 <= yw12[13:12]; z12 <= zw12; end endmodule