// Test pattern generator for DAC902
// push 16 values in via host, this block will address them at 80 MS/s

`timescale 1ns / 1ns
// module srl16x12e(Q, A0, A1, A2, A3, CE, CLK, D);
//  see srl16x12e.pl

module dac_testpattern(clk80, dac_out, load_data, clk_host, we);
	input  clk80, clk_host, we;
	wire   clk80, clk_host, we;
	output [11:0] dac_out;
	reg    [11:0] dac_out;
	input  [15:0] load_data;
	wire   [15:0] load_data;
	reg [3:0] cnt;
	always @(posedge clk80) cnt <= cnt + 1'b1;
`ifdef SIMULATE
	initial cnt = 0;
`endif
	wire [11:0] srl_out;
	srl16x12e bank(.Q(srl_out), .A0(cnt[0]), .A1(cnt[1]), .A2(cnt[2]),  .A3(cnt[3]),
		.CE(we), .CLK(clk_host), .D(load_data[15:4]));
	always @(posedge clk80) dac_out <= srl_out;
endmodule