// Setpoint waveform generation for LLRF
// Larry Doolittle, LBNL, December 2002 - January 2003

// Given the 40 MHz clock and a vector setpoint, creates
// the steady 10 MHz (a.k.a. 50 MHz) waveform.  If compiled
// with full DDS support, that frequency can be adjusted,
// and of course in that case the initial phase of the result
// is not terribly important.

// Testing should verify that when the input freq is zero,
// the phase of the output waveform is the same for the two
// compilation options.  The discrepancy during the cordic
// pipeline fill time can be ignored.

// Note that the CORDIC routine scales the output by the usual
// factor of 1.64676.  This introduces an incompatibility between
// the fixed and adjustable frequency configurations.  The output
// signal "unadjustable" is intended to be passed through to some
// upper level of software, that can then take this into account.

// 16-bit input freq is a signed number, full scale is +/- 625 kHz,
// so one bit is 19.073486328125 Hz.

`timescale 1ns / 1ns

// `define DDS_UNADJUSTABLE

module dds(clk, wave, set_i, set_q, sync, freq, unadjustable);

input clk, sync;
input [13:0] set_i, set_q;
input [15:0] freq;   // ignored if DDS_UNADJUSTABLE
output [13:0] wave;
output unadjustable;












assign unadjustable = 1'b0;
reg [20:0] phase;
wire [15:0] wave16;

// The cordic routine now uses 16-bits internally, to improve
// internally generated roundoff and truncation error.
// But set_i, set_q, and wave are all 14-bit quantities.  Cope.
cordic c(clk, {set_i,2'b00}, {set_q,2'b00}, phase[20:4], wave16, ,);
assign wave=wave16[15:2];

// add the signed freq to 10 MHz
//                    20.0   10.0      5.0       2.5       1.25      0.625
wire [20:0] dphase = {1'b0, ~freq[15], freq[15], freq[15], freq[15], freq};
always @(posedge clk) begin
	phase <= sync ? phase+dphase : 0;
end
// always @(negedge clk) $display("%d %d",$time,phase);


endmodule