`timescale 1ns / 1ns

`define DAC902

module error3(
SATURATED,
t_mod_4,
FDBK_EN,
CLK,
ERR3,
ERR4,
dkcm_bus,
dkcm_clk
);

input  [9:0]  SATURATED;
input  [20:0] dkcm_bus;
input   dkcm_clk;
input  [1:0]  t_mod_4;
input   FDBK_EN;   // feedback enable
input   CLK;
output [11:0] ERR3;
output [11:0] ERR4;
reg    [11:0] ERR4;

// internal signals declaration
reg [9:0] ERR1;       // registered saturated error
reg [9:0] ERR2;       // delayed version of ERR1
reg [12:0] ERR3_loc;  // proportional error term, before passing to port
wire [23:0] PROD1, PROD2, PROD3;
wire [12:0] SUM;
reg [11:0] ADD2;   // the adder

  // Input pipeline: ERR2 has a 90 degree phase lag from ERR1
  always @(posedge CLK) begin
    ERR1 <= SATURATED;
    ERR2 <= ERR1;
  end

  // Three loadable Constant Coefficient Multipliers (KCM)
  // Note the unique three-bit addresses (ident)
  dkcm_bussed MUL1( .var({ERR1,2'b00}), .product(PROD1),
    .clk(dkcm_clk), .dkcm_bus(dkcm_bus), .ident(3'b001));

  dkcm_bussed MUL2( .var({ERR2,2'b00}), .product(PROD2),
    .clk(dkcm_clk), .dkcm_bus(dkcm_bus), .ident(3'b010));

  dkcm_bussed MUL3( .var(ERR3_loc[12:1] ), .product(PROD3),
    .clk(dkcm_clk), .dkcm_bus(dkcm_bus), .ident(3'b011));

  // to avoid wrap-around after addition, arguments are resized
  // one bit larger before addition is performed.
  assign SUM = {PROD1[23] ,PROD1[23:12]} + {PROD2[23] ,PROD2[23:12]};

`ifdef DAC902
  wire sign_flip = 1'b0;
`else
  wire sign_flip = t_mod_4[1];
`endif
  always @(posedge CLK) begin
    // if t < intial ramp time ... feedback not enabled 
    // I at input when t_mod_4 = "00", Q when "01", -I when "10", -Q when "11"
    // we want the feedback output to be I, Q, I, Q, I, Q, ... 
    ERR3_loc <= FDBK_EN ? (sign_flip ? -SUM : SUM) : {13{1'b0}};
    // slice and register upper 12 bits from KCM output
    ERR4 <= PROD3[23:12] ;
  end

  assign ERR3 = ERR3_loc[12:1] ;

endmodule