// Flashes with 12.5% duty factor if err is present,
// or 87.5% duty factor if err is not present.
// total period of flashing is the combination of all three counters,
// 11 + 10 + 3 = 24 bits
// 25 MHz / 2^24 = 1.49 Hz

`timescale 1ns / 1ns

module flasher(clk, err, lampo);
	input clk, err;
	output lampo;
	reg    lampo;
	reg [10:0] c1;
	reg  [9:0] c2;
	reg  [2:0] c3;
	reg c1z, c2z, trip;
`ifdef SIMULATE
	initial begin c1=0; c2=0; c3=0; trip=0; end
`endif
	always @(posedge clk) begin
		c1 <= c1 + 1;
		c1z <= c1==0;
		if (c1z) c2 <= c2 + 1;
		c2z <= c1z & (c2==0);
		if (c2z) c3 <= c3 + 1;
		trip <= (trip & ~(c2z & c3==1)) | err;
		if (c2z) lampo <= c3[2] ? ( c3[1] ? (c3[0]?0:lampo) : lampo)
		                        : ( c3[1] ? lampo : (c3[0]?~trip:1) );
	end
endmodule