// LLRF history buffers for test submodule
// Larry Doolittle, LBNL, March 2003
// See history.v for its care and feeding
// 512 x 16 buffer, programmable averaging

`timescale 1ns / 1ns

module hist2(
	clk40, in_data, trace_address, write_enable, clear, keep_mux,
	clk_host, host_dout, host_addr);
input  clk40;
input  [11:0] in_data;
input  [8:0] trace_address;
input  [2:0]  keep_mux;
input  write_enable, clear;
input  clk_host;
output [15:0] host_dout;
input  [8:0] host_addr;

wire [18:0] recirc;
// sign extend from 12 to 19 bits
wire [18:0] extend_in = {{7{in_data[11]}},in_data};
wire [18:0] sum = clear ? extend_in : (extend_in-recirc);
wire [15:0] keep = {sum[15:3],
	keep_mux[2] ? sum[18] : sum[2],
	keep_mux[1] ? sum[17] : sum[1],
	keep_mux[0] ? sum[16] : sum[0]};

ramdp512x16 trace1(
	.ADDRA(trace_address),
	.RSTA(1'b0),
	.ENA(1'b1),
	.WEA(write_enable),
	.CLKA(clk40),
	.DIA(keep),
	//.DOA(void), // read from host
	.ADDRB(host_addr),
	.RSTB(1'b0),
	.ENB(1'b1),
	.WEB(1'b0), // host write not allowed
	.CLKB(clk_host),
	.DIB(16'd0), // not used
	.DOB(host_dout));

// two-deep FIFO
srl16x19e fifo(
	.Q(recirc), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0),
	.CE(write_enable), .CLK(clk40), .D(sum));

endmodule