// Verilog ramdp2048x14 definition
// No copyright is claimed on this machine-generated code.
// Automatically generated from perl bram.pl 14 11
// bram.pl is Copyright (C) 2002 Larry Doolittle <larry@doolittle.boa.org>

// 2048 x 14 dual port RAM, aggregated from
// 7 instances of 2048 x 2 Virtex Block RAM

`timescale 1ns / 1ns

module ramdp2048x14(
	ADDRA, RSTA, ENA, WEA, CLKA, DIA, DOA,
	ADDRB, RSTB, ENB, WEB, CLKB, DIB, DOB);

input  [10:0] ADDRA;
input  RSTA, ENA, WEA, CLKA;
input  [13:0] DIA;
output [13:0] DOA;

input  [10:0] ADDRB;
input  RSTB, ENB, WEB, CLKB;
input  [13:0] DIB;
output [13:0] DOB;

wire   [10:0] ADDRA;
wire   RSTA, ENA, WEA, CLKA;
wire   [13:0] DIA;
wire   [13:0] DOA;

wire   [10:0] ADDRB;
wire   RSTB, ENB, WEB, CLKB;
wire   [13:0] DIB;
wire   [13:0] DOB;

RAMB4_S2_S2 b0(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[1:0]),
	.DOA   (DOA[1:0]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[1:0]),
	.DOB   (DOB[1:0])
);

RAMB4_S2_S2 b1(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[3:2]),
	.DOA   (DOA[3:2]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[3:2]),
	.DOB   (DOB[3:2])
);

RAMB4_S2_S2 b2(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[5:4]),
	.DOA   (DOA[5:4]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[5:4]),
	.DOB   (DOB[5:4])
);

RAMB4_S2_S2 b3(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[7:6]),
	.DOA   (DOA[7:6]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[7:6]),
	.DOB   (DOB[7:6])
);

RAMB4_S2_S2 b4(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[9:8]),
	.DOA   (DOA[9:8]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[9:8]),
	.DOB   (DOB[9:8])
);

RAMB4_S2_S2 b5(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[11:10]),
	.DOA   (DOA[11:10]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[11:10]),
	.DOB   (DOB[11:10])
);

RAMB4_S2_S2 b6(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[13:12]),
	.DOA   (DOA[13:12]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[13:12]),
	.DOB   (DOB[13:12])
);

endmodule