// Verilog ramdp4096x12 definition
// No copyright is claimed on this machine-generated code.
// Automatically generated from perl bram.pl 12 12
// bram.pl is Copyright (C) 2002 Larry Doolittle <larry@doolittle.boa.org>

// 4096 x 12 dual port RAM, aggregated from
// 12 instances of 4096 x 1 Virtex Block RAM

`timescale 1ns / 1ns

module ramdp4096x12(
	ADDRA, RSTA, ENA, WEA, CLKA, DIA, DOA,
	ADDRB, RSTB, ENB, WEB, CLKB, DIB, DOB);

input  [11:0] ADDRA;
input  RSTA, ENA, WEA, CLKA;
input  [11:0] DIA;
output [11:0] DOA;

input  [11:0] ADDRB;
input  RSTB, ENB, WEB, CLKB;
input  [11:0] DIB;
output [11:0] DOB;

wire   [11:0] ADDRA;
wire   RSTA, ENA, WEA, CLKA;
wire   [11:0] DIA;
wire   [11:0] DOA;

wire   [11:0] ADDRB;
wire   RSTB, ENB, WEB, CLKB;
wire   [11:0] DIB;
wire   [11:0] DOB;

RAMB4_S1_S1 b0(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[0:0]),
	.DOA   (DOA[0:0]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[0:0]),
	.DOB   (DOB[0:0])
);

RAMB4_S1_S1 b1(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[1:1]),
	.DOA   (DOA[1:1]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[1:1]),
	.DOB   (DOB[1:1])
);

RAMB4_S1_S1 b2(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[2:2]),
	.DOA   (DOA[2:2]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[2:2]),
	.DOB   (DOB[2:2])
);

RAMB4_S1_S1 b3(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[3:3]),
	.DOA   (DOA[3:3]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[3:3]),
	.DOB   (DOB[3:3])
);

RAMB4_S1_S1 b4(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[4:4]),
	.DOA   (DOA[4:4]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[4:4]),
	.DOB   (DOB[4:4])
);

RAMB4_S1_S1 b5(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[5:5]),
	.DOA   (DOA[5:5]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[5:5]),
	.DOB   (DOB[5:5])
);

RAMB4_S1_S1 b6(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[6:6]),
	.DOA   (DOA[6:6]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[6:6]),
	.DOB   (DOB[6:6])
);

RAMB4_S1_S1 b7(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[7:7]),
	.DOA   (DOA[7:7]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[7:7]),
	.DOB   (DOB[7:7])
);

RAMB4_S1_S1 b8(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[8:8]),
	.DOA   (DOA[8:8]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[8:8]),
	.DOB   (DOB[8:8])
);

RAMB4_S1_S1 b9(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[9:9]),
	.DOA   (DOA[9:9]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[9:9]),
	.DOB   (DOB[9:9])
);

RAMB4_S1_S1 b10(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[10:10]),
	.DOA   (DOA[10:10]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[10:10]),
	.DOB   (DOB[10:10])
);

RAMB4_S1_S1 b11(
	.ADDRA (ADDRA),
	.RSTA  (RSTA),
	.ENA   (ENA),
	.WEA   (WEA),
	.CLKA  (CLKA),
	.DIA   (DIA[11:11]),
	.DOA   (DOA[11:11]),

	.ADDRB (ADDRB),
	.RSTB  (RSTB),
	.ENB   (ENB),
	.WEB   (WEB),
	.CLKB  (CLKB),
	.DIB   (DIB[11:11]),
	.DOB   (DOB[11:11])
);

endmodule