`timescale 1ns / 1ns
module main();

reg [11:0] adca, adcb, adcc, adcd;

adctest fpga(
	.DA(adca), .DAOV(1'b0), .DB(adcb), .DBOV(1'b0),
	.DC(adcc), .DCOV(1'b0), .DD(adcd), .DDOV(1'b0),
	.CLK(clk),
	.P_Down(P_Down), // Output pin to power down the bank of ADCs 
	.RF_ON(RF_ON), .RF_KILL(RF_KILL), .IL_STAT(IL_STAT),
	.CLK80X(clk80), .DE(DE), .SLEEP(SLEEP),  // 80 MS/s DAC
	.PD(PD[15:0]), // 16-bit bi-directional data bus
	.ALE_host(ALE_host), .WE_host(WE_host), .RD_host(RD_host),
        .CS0_host(CS0_host), .RDY_host(RDY_host), .CK_host(CK_host),
	.INT_host(INT_host),
	.SCLK(SCLK), .SDIN(SDIN), .DOUT1202(DOUT1202),
	.SDA75(SDA75), .CS1202(CS1202), .CS5742(CS5742),
	.DS2401(DS2401),
	.PLL_CLK(PLL_CLK), .PLL_DATA(PLL_DATA), .PLL_LE(PLL_LE),
	.PLL_MUXOUT(PLL_MUXOUT), .PLL_CE(PLL_CE),
	.LED2(led2), .LED3(led3), .LED4(led4),
	.DIO1(DIO1), .DIO2(DIO2), .DIO3(DIO3), .DIO4(DIO4)
);

reg clk, clk80;
wire P_Down;
reg RF_ON;  initial RF_ON = 0;
wire RF_KILL, IL_STAT, SLEEP;
wire [11:0] DE;
wire [31:0] PD;
wire ALE_host, WE_host, RD_host, CS0_host, CK_host;
wire RDY_host, INT_host;
wire SCLK, SDIN, DOUT1202, SDA75, CS1202, CS5742;
wire DS2401;
wire PLL_CLK, PLL_DATA, PLL_LE, PLL_CE;
wire led2, led3, led4, DIO1, DIO2, DIO3, DIO4;

// 40 MHz RF clk
integer cc;
initial begin
  $dumpfile("llrf.vcd");
  $dumpvars(5,main);
  $display("Hello, World.");
  for (cc = 0; cc < 4000; cc = cc + 1) begin
     // $display("RF cycle %d",cc);
        clk80=1; #3; clk=1; #3; clk80=0; #6;
        clk80=1; #3; clk=0; #3; clk80=0; #6;
     // if (cc==400) RF_ON = 1;
  end
end

initial begin
	adca = 0;
	adcb = 0;
	adcc = 0;
	adcd = 0;
end
always @(negedge clk) begin
	adca <= adca + 16;
	adcb <= adcb + 20;
	adcc <= adcc + 24;
	adcd <= adcd + 28;
end

// always @(posedge OCLK) if (RF_ON) begin
//	$llrf_sysmodel(DAC_out, OSEL, adca, adcb, adcc);
// end

nanoengine host(PD, CK_host, ALE_host, CS0_host, WE_host, RD_host, INT_host);

always @(negedge INT_host) begin
  $display("Need to emulate interrupt routine");
end

// oversimplified model of ADF4001
reg [23:0] pll_sr = 0;
reg PLL_MUXOUT = 0;
always @(posedge PLL_CLK) begin
	pll_sr <= {pll_sr[22:0], PLL_DATA};
	PLL_MUXOUT <= 1'bx;
	#20;
	PLL_MUXOUT = pll_sr[23];
end
endmodule