`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk;
	reg host_write;
	reg [15:0] write_bus = 8'b11110010;   // reset
	initial begin
		$dumpfile("adf4xxx.vcd");
		$dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 330; cc = cc + 1) begin
			clk = 1; #20;
			host_write = cc%30==20;
			if (cc ==   1) begin write_bus = 12'h300; end  // 1->LE 1->CE
			if (cc ==  31) begin write_bus = 12'h200; end  // 0->LE
			if (cc ==  61) begin write_bus = 12'h655; end  // byte 1 (msb)
			if (cc ==  91) begin write_bus = 12'h617; end  // byte 2
			if (cc == 121) begin write_bus = 12'h6aa; end  // byte 3 (lsb)
			if (cc == 151) begin write_bus = 12'h300; end  // 1->LE
			if (cc == 181) begin write_bus = 12'h200; end  // 0->LE
			if (cc == 211) begin write_bus = 12'h655; end  // byte 1 (msb)
			if (cc == 241) begin write_bus = 12'h617; end  // byte 2
			if (cc == 271) begin write_bus = 12'h6aa; end  // byte 3 (lsb)
			if (cc == 301) begin write_bus = 12'h300; end  // 1->LE
			clk = 0; #20;
		end
	end

	wire [15:0] read_bus;
	wire sclk, sdata, le, ce;

	reg [23:0] chip_sr = 0;
	reg muxout;
	always @(posedge sclk) begin
		chip_sr <= {chip_sr[22:0], sdata};
		muxout <= 1'bx;
		#20;
		muxout = chip_sr[23];
	end

	adf4xxx chip( clk, sclk, sdata, le, muxout, ce,
		host_write, write_bus[10:0], read_bus);
endmodule