// X_CLKDLL doubler(.CLKIN(clk40), .LOCKED(dll_locked), .CLK2X(clk80t),
// 	.CLKFB(clk40t), .CLK0(clk40t));

// BUFG b1(clk80, clk80t);

`timescale 1ns / 1ns
module main();

integer cc;
reg clk_host, clk40, clk80, load;
reg signed [11:0] sig_in, sig_in1, sig_in2, sig_in3;
wire [20:0] dkcm_bus;

initial begin
	$dumpfile("afterburner.vcd");
	$dumpvars(4,main);
	for (cc = 0; cc < 300; cc = cc + 1) begin
		clk_host = 1; #20;
		clk_host = 0; #20;
		load = (cc==10);
	end
	$finish;
end

always begin
	clk80=1; #3; clk40=1; #3; clk80=0; #6;
	clk80=1; #3; clk40=0; #3; clk80=0; #6;
end

reg signed [11:0] konstant = -1448;  // 2048/sqrt(2)
wire busy;
dkcm_controller mut(clk_host, dkcm_bus, konstant, load, 3'b000, busy);

wire [11:0] dac_out;
reg signed [11:0] dac_outr;
afterburner dut(clk40, sig_in, clk80, dac_out, clk_host, dkcm_bus);
always @(dac_out) begin
	dac_outr = dac_out;
	$display("dac %d",dac_outr);
end

initial begin
	sig_in  <= 1200;
	sig_in1 <= 1200;
	sig_in2 <= -1200;
	sig_in3 <= -1200;
end
always @(posedge clk40) begin
	sig_in  <= sig_in1;
	sig_in1 <= sig_in2;
	sig_in2 <= sig_in3;
	sig_in3 <= sig_in;
end

endmodule