`timescale 1ns/100ps
module test();

reg myclk;
reg [2:0] myhost_addr; 
reg myhost_write; 
reg [15:0] mywrite_bus;
wire [15:0] myread_bus;
wire mySCLK;
reg mySDIN;
wire myDOUT1202; 
wire mySDA75;
wire myCS1202; 
wire myCS5742;
wire myPLL_CLK; 
wire myPLL_DATA; 
wire myPLL_LE;
wire myPLL_MUXOUT; 
wire myPLL_CE;
reg myreset;
reg [15:0] cc;

initial 
	begin
		$dumpfile("altsport.vcd");
		$dumpvars(5,test);
		myclk = 0;
		forever #20 myclk = !myclk;
	end

initial cc = 0;
initial 
	begin 
		myhost_write <= 0;
		cc <= 0;
		while (cc < 1000)
			begin @ (posedge myclk)
				if (cc == 0) myreset <= 0;
				if (cc == 1) myreset <= 1;
				if (cc == 2) myreset <= 0;
				if (cc == 9)
				begin
					myhost_addr <= 3'b000;
					mywrite_bus <= 16'b1000001100000000;
					myhost_write <= 1;
				end
				if (cc == 10) myhost_write <= 0;
		
				cc <= cc + 1;
			end
		cc <= 0;

					
		while (cc < 10000)
			begin @ (posedge myclk)
				if (cc == 0) myreset <= 0;
				if (cc == 1) myreset <= 0;
				if (cc == 2) myreset <= 0;
				if (cc == 9) 
				begin
					myhost_addr <= 3'b011;
					myhost_write <= 1;
					mywrite_bus <= 16'b1010111000000000;
				end
				if (cc == 10) myhost_write <= 0;
				if (cc == 2500) 
				begin
					myhost_addr <= 3'b011;
					myhost_write <= 1;
					mywrite_bus <= 16'b1010101000000001;
				end
				if (cc == 2501) myhost_write <= 0;
				if (cc == 5000) 
				begin
					myhost_addr <= 3'b011;
					myhost_write <= 1;
					mywrite_bus <= 16'b1010011000000010;
				end
				if (cc == 5001) myhost_write <= 0;
				cc <= cc + 1;
			end
		cc <= 0;
		while (cc < 30000)		
			begin @ (posedge myclk)
				
				if (cc == 0)
				myreset <= 0;
				if (cc == 1)
				myreset <= 1;
				if (cc == 2)
				myreset <= 0;
				if (cc == 9)
				begin
						myhost_addr <= 3'b100;
						myhost_write <= 1;					   
						mywrite_bus <= 16'h4802;
					end
				if (cc == 10) myhost_write <= 0;
				
				if (cc == 5500) myreset <= 0;
				if (cc == 5501) myreset <= 0;
				if (cc == 5502) 
					begin
						myhost_write <= 1;
						mywrite_bus <= 16'h0006;
						myhost_addr <= 3'b100;
					end
				if (cc == 5503)
					myhost_write <= 0;

				if (cc == 11000) 
					myreset <= 0;
				
				if (cc == 11001)
					myreset <= 0;
			
				if (cc == 11002)
					begin
						myhost_write <= 1;
						mywrite_bus <= 16'h4882;
						myhost_addr <= 3'b100;
					end
				if (cc == 11003)
					myhost_write <= 0;

				if (cc == 17500)
					myreset <= 0;
				
				if (cc == 17501)
					myreset <= 0;
			
				if (cc == 17502)
					begin
						myhost_write <= 1;
						mywrite_bus <= 16'h0004;
						myhost_addr <= 3'b100;
					end
				if (cc == 17503)
					myhost_write <= 0;
				
				if (cc == 23000)
					myreset <= 0;
				
				if (cc == 23001)
					myreset <= 0;
				
				if (cc == 23002)
					begin
						myhost_write <= 1;
						mywrite_bus <= 16'h0000;
						myhost_addr <= 3'b100;
					end
			  if (cc == 23003)
					myhost_write <= 0;	
				if (cc == 29000)
					myreset <= 0;
				if (cc == 29001)
					myreset <= 0;
				if (cc == 29050)
					begin
						myhost_write <= 1;
						myhost_addr <= 3'b011;
					end
				if (cc == 29051)
					myhost_write <= 0;
			  cc <= cc + 1;
			end
			cc <= 0;
		myhost_write <= 0;
		
		$finish;
		
			
	end
		
	altsport s(.clk(myclk), .host_addr(myhost_addr), .host_write(myhost_write), .write_bus(mywrite_bus),
			 .read_bus(myread_bus), .SCLK(mySCLK),
		//	 .SDIN(mySDIN), .DOUT1202(myDOUT1202),
			 .SDIN(myDOUT1202), .DOUT1202(mySDIN),
			 .SDA75(mySDA75), .CS1202(myCS1202), .CS5742(myCS5742),
			 .PLL_CLK(myPLL_CLK), .PLL_DATA(myPLL_DATA), .PLL_LE(myPLL_LE), .PLL_MUXOUT(myPLL_MUXOUT), .PLL_CE(myPLL_CE), .reset(myreset));
	
endmodule