// plot "< grep -v x foo" using 1:(($3-sin($1*pi/16384)*6746)/4)
// plot "< grep -v x foo" using 1:(($2-cos($1*pi/16384)*6746)/4)
//
// plot "< grep -v x cordic.dat" using 1:(($2-cos($1*pi/65536)*16384*1.64676)/4)

`timescale 1ns / 1ns

module main();

reg clk;
initial clk=0;
initial begin
	// $dumpfile("cordic.vcd");
	// $dumpvars(5,main);
	clk = 0;
	forever #10 clk=~clk;
end

integer cc;
initial begin
	cc = 0;
	while (cc < 8220) @(posedge clk) cc<=cc+1;
	$finish;
end
reg [15:0] xin=16'b0100000000000000;
reg [15:0] yin=16'b0000000000000000;
reg [16:0] phasein=0;
always @(posedge clk) phasein<=phasein+17;
wire [15:0] xout, yout;
wire [0:0] pout;
cordic dut(clk, xin, yin, phasein, xout, yout, pout);
reg signed [15:0] xxout, yyout, ppout;
reg signed [16:0] p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16;
always @(posedge clk) begin
	xxout = xout;
	yyout = yout;
	ppout = pout;
	// Match the pipeline delay inside cordic.
	// You know when the lengths match when column 1 and 2 both become
	// non-x at the same time.
	p16<=p15; p15<=p14; p14<=p13; p13<=p12; p12<=p11; p11<=p10;
	p10<=p9; p9<=p8; p8<=p7; p7<=p6; p6<=p5;
	p5<=p4; p4<=p3; p3<=p2; p2<=p1; p1<=phasein;
	$display("%6d %6d %6d %6d", p16, xxout, yyout, ppout);
end
endmodule