`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk;
	reg host_write;
	initial begin
		$dumpfile("ds2401.vcd");
		$dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 600; cc = cc + 1) begin
			host_write = (cc== 10) | (cc==50) |
			             (cc==200) | (cc==350);
			if (cc == 15)  write_bus = 4'b1101;  // exit reset
			if (cc == 60)  write_bus = 4'b1001;  // transmit '1'
			if (cc == 220) write_bus = 4'b0001;  // transmit '0'
			clk = 1; #20;
			clk = 0; #20;
		end
	end

	reg [3:0] write_bus = 4'b0010;   // reset
	wire [15:0] read_bus;
	wire dallas_pin;
	wire dallas_rcv = (dallas_pin!==0);

	integer bit_count;
	initial bit_count=0;
	reg dallas_chip_drive=0;
	always @(negedge dallas_rcv) begin
		bit_count = bit_count+1;
		dallas_chip_drive = 1'b1;
		#1560;
		dallas_chip_drive = 1'bx;
		#1560;
		dallas_chip_drive = 1'b0;
	end
	assign dallas_pin = dallas_chip_drive ? 1'b0 : 1'bz;

	ds2401 fpga( clk, dallas_pin, host_write, write_bus, read_bus);
endmodule