`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk, load;
	reg signed [11:0] konstant;
	reg  [2:0] addr;
	initial begin
		// $dumpfile("fdbk_loop.vcd");
		// $dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 500; cc = cc + 1) begin
			#20;
			clk = 1;
			#20;
			clk = 0;
			load = (cc%40 == 10) && (cc<100);
			if (cc ==  5) begin konstant=2047; addr=1; end  // real
			if (cc == 45) begin konstant=   0; addr=2; end  // imag
			if (cc == 85) begin konstant=1024; addr=3; end  // integral
		end
		$finish;
	end
	wire [20:0] dkcm_bus;
	wire busy;
	dkcm_controller mut(clk, dkcm_bus, konstant, load, addr, busy);

	reg clk40;
	always begin
		clk40=1;  #12;
		clk40=0;  #13;
	end

	reg [1:0] sync_count;  initial sync_count=0;
	always @(posedge clk40) sync_count <= sync_count+1;

	reg signed [11:0] adc_input;
	wire [11:0] output40;
	reg [13:0] iq, set_wave;
	initial adc_input=-20; // simple DC offset
	reg feedback_on, integrate_on;
	initial feedback_on=0; initial integrate_on=0;
	
	always @(posedge clk40) begin
		feedback_on  <= (cc>120);
		integrate_on <= (cc>180);
		iq = sync_count[0] ? 13'd128 : 0;
		set_wave <= sync_count[1] ? iq : -iq;
	end

	fdbk_loop fdbk(
		.M(adc_input), .set_wave(set_wave),
		.dkcm_bus(dkcm_bus), .dkcm_clk(clk),
		.feedback_enable(feedback_on), .integrate_enable(integrate_on),
		.feedforward_data(8'b0),
		.CLK(clk40), .t_mod_4(sync_count),
		.fdbk_err_out(output40));

	reg signed [11:0] output40_signed;
	always @(posedge clk40) begin
		if (cc > 100) begin
			output40_signed = output40;
			$display("feedback output %d", output40_signed);
		end
	end

endmodule