`timescale 1ns / 1ns

module main();

reg [6:0] average;
reg [14:0] stop_count;
reg [2:0] keep_mux;
integer pulse_len;
reg [11:0] trace_mem[0:4095];

initial begin
	if (!$value$plusargs("pulse_len=%d",  pulse_len))  pulse_len=4076;
	if (!$value$plusargs("average=%d",    average))    average=0;
	if (!$value$plusargs("stop_count=%d", stop_count)) stop_count=-1;
	if (!$value$plusargs("keep_mux=%d",   keep_mux))   keep_mux=0;
	$readmemh("given.dat", trace_mem);
	$display("pulse_len %d",  pulse_len);
	$display("average %d",    average);
	$display("stop_count %d", stop_count);
	$display("keep_mux %d",   keep_mux);
end

integer cc;
reg clk40, clk_host;
initial begin
	clk_host = 0;
	for (cc=0; cc<(pulse_len+20); cc=cc+1) begin
		clk40 = 0; #12;
		clk40 = 1; #13;
	end
	for (cc=0; cc<513; cc=cc+1) begin
		clk_host = 0; #20;
		clk_host = 1; #20;
	end
	$display("cnt_at_pulse_end %d", cnt_at_pulse_end);
end

reg trace_enable;
reg [11:0] trace_temp;
reg signed [11:0] trace_data;
always @(posedge clk40) begin
	// trace_data <= $random;
	trace_temp = trace_mem[cc];
	trace_data <= {~trace_temp[11],trace_temp[10:0]};
	trace_enable <= (cc>=10) & (cc<(pulse_len-10));
	if (trace_enable) $display("input %d %d", cc, trace_data);
end

reg [13:0] host_addr = 0;
wire [15:0] host_dout;
reg signed [15:0] host_douts;
always @(posedge clk_host) begin
	host_addr <= host_addr+1;
	host_douts = host_dout;
	$display("memory %d %d", host_addr-1, host_douts);
end

wire rstn = 1'b1;
wire [14:0] cnt_at_pulse_end;

wire [8:0] trace_address;
wire write_enable, avg_clear;
hist2 trace3(
	clk40, trace_data, trace_address, write_enable, avg_clear, keep_mux,
	clk_host, host_dout, host_addr[8:0]);

histmode uhm(
	clk40, rstn, trace_enable, average, stop_count,
	trace_address, write_enable, avg_clear, cnt_at_pulse_end);

endmodule

module glbl();
	wire GSR = 0;
endmodule