`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk;
	reg load;
	initial begin
		$dumpfile("kcm.vcd");
		$dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 600; cc = cc + 1) begin
			#20;
			clk = 1;
			#20;
			clk = 0;
			load = (cc%60 == 10);
			if (load) konstant = 12'h700;
		end
	end
	reg [11:0] konstant;  initial konstant=2000;
	reg  [2:0] addr;      initial addr=3;
	wire [20:0] dkcm_bus;
	wire busy;
	dkcm_controller mut(clk, dkcm_bus, konstant, load, addr, busy);

	reg signed [11:0] var;  initial var=0;
	reg signed [11:0] konstant2;
	always @(posedge clk) begin
		var <= ($random&1'b1) ? 12'h7fc : 12'h800;
	end
	wire [23:0] product;
	dkcm_bussed t(var, product, clk, dkcm_bus, 3'b011);
	reg signed [23:0] answer;
	always @(negedge clk) begin
		if (busy) konstant2 <= konstant;
		if (~busy) begin
			answer = product;
			$display("r=check( %d, %d, %d)",var, konstant2, answer);
		end
	end
endmodule