`timescale 1ns / 1ns
module main();

reg [11:0] adca, adcb, adcc;

DESIGN_TOP fpga(
	.DA(adca), .DAOV(1'b0), .DB(adcb), .DBOV(1'b0),
	.DC(adcc), .DCOV(1'b0), .DD(12'b0), .DDOV(1'b0),
	.SYNC(1'b0), .GLOBAL_RST(1'b0), .CLK(clk),
	.P_Down(P_Down), // Output pin to power down the bank of ADCs 
	.RF_ON(RF_ON), .RF_KILL(RF_KILL),
	.PD(PD[15:0]), // 16-bit bi-directional data bus
	.ALE_host(ALE_host), .WE_host(WE_host), .RD_host(RD_host),
        .CS0_host(CS0_host), .RDY_host(RDY_host), .CK_host(CK_host),
	.URST(1'b0), .INT_host(INT_host),
	.DE(DAC_out), .OCLK(OCLK), .OSEL(OSEL), .SLEEP(SLEEP),
	.SP_DOUT(sp_dout), .SP_DIN(sp_din), .SP_SCLK(sp_sclk),
	.SP_CS1(sp_cs1), .SP_CS2(sp_cs2), .SP_CS3(sp_cs3), .SP_CS4(sp_cs4),
	.TEST_1(test_1), .TEST_2(test_2), .TEST_3(test_3), .TEST_4(test_4)
);

reg clk;
wire P_Down;
reg RF_ON;  initial RF_ON = 0;
wire RF_KILL;
wire [31:0] PD;
wire ALE_host, WE_host, RD_host, CS0_host, CK_host;
wire RDY_host, INT_host;
wire [11:0] DAC_out;
wire OCLK, OSEL, SLEEP;
reg  sp_dout=0;      // need to attach simulation of external device
wire sp_din, sp_sclk;
wire sp_cs1, sp_cs2, sp_cs3, sp_cs4;
wire test_1, test_2, test_3, test_4;

// 40 MHz RF clk
integer cc;
initial begin
  $dumpfile("llrf.vcd");
  $dumpvars(5,main);
  $display("Hello, World.");
  for (cc = 0; cc < 4000; cc = cc + 1) begin
     $display("RF cycle %d",cc);
     clk = 1; #13;
     clk = 0; #12;
     if (cc==400) RF_ON = 1;
  end
end

always @(posedge OCLK) if (RF_ON) begin
	$llrf_sysmodel(DAC_out, OSEL, adca, adcb, adcc);
end

nanoengine host(PD, CK_host, ALE_host, CS0_host, WE_host, RD_host, INT_host);

always @(negedge INT_host) begin
  $display("Need to emulate interrupt routine");
end
endmodule