`timescale 1ns / 1ns
module main();

wire [31:0] bus;
reg INT=0;
wire CLK, ALE, CS0, WE, RD;
nanoengine host(bus, CLK, ALE, CS0, WE, RD, INT);

initial begin
	$dumpfile("nanoengine.vcd");
	$dumpvars(5,main);
	$display("Hello, World.");
end

always @(negedge INT) begin
  $display("Need to emulate interrupt routine");
end
endmodule