`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk;
	reg host_write;
	initial begin
		$dumpfile("sport1.vcd");
		$dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 1000; cc = cc + 1) begin
			host_write = (cc== 20) | (cc==520);
			if (cc == 15)  write_bus = 16'h1234;
			if (cc == 415)  write_bus = 16'h5a5a;
			clk = 1; #20;
			clk = 0; #20;
		end
	end

	reg [15:0] write_bus;   // reset
	wire [15:0] read_bus;
	wire sclk, dout, cs;
	reg din;

	sport1 chip( clk, host_write, write_bus, read_bus,
		sclk, din, dout, cs);

	always @(posedge sclk) begin
		din <= 1'bx;
		#10;
		din <= $random();
	end
endmodule