`timescale 1ns / 1ns
module main();
	integer cc;
	reg clk;
	reg addr, host_write;
	reg [15:0] write_bus = 8'b11110010;   // reset
	initial begin
		$dumpfile("sportx.vcd");
		$dumpvars(4,main);
		// 25 MHz clk
		for (cc = 0; cc < 4200; cc = cc + 1) begin
			clk = 1; #20;
			if (cc<500) host_write = (cc%50==20);
			if (cc>1000 && cc<1200) host_write = (cc%50==20);
			if (cc>2000 && cc<2100) host_write = (cc%50==20);
			if (cc>3000 && cc<3100) host_write = (cc%50==20);
			if (cc>4000 && cc<4100) host_write = (cc%50==20);
			// exercise the ADF4001  devsel=2'b00
			if (cc ==   1) begin write_bus = 16'h00b4; addr=1; end  // 1->LE 1->CE
			if (cc ==  51) begin write_bus = 16'h1234; addr=0; end  // junk data
			if (cc == 101) begin write_bus = 16'h0095; addr=1; end  // 0->LE 1->CE
			if (cc == 151) begin write_bus = 16'h00b4; addr=1; end  // 0->LE 1->CE
			// exercise the MAX5742  devsel=2'b11
			if (cc == 201) begin write_bus = 16'h1234; addr=0; end  // junk data
			if (cc == 251) begin write_bus = 16'h0037; addr=1; end  // 0->CS
			if (cc == 301) begin write_bus = 16'h00b6; addr=1; end  // 1->CS
			// exercise the MAX1202  devsel=2'b00
			if (cc == 351) begin write_bus = 16'h3456; addr=0; end  // junk data
			if (cc == 401) begin write_bus = 16'h00b0; addr=1; end  // select first
			if (cc == 451) begin write_bus = 16'h00b1; addr=1; end  // CS takes care of itself
			// exercise the TCN75    devsel=2'b01
			if (cc == 1001) begin write_bus = 16'h0400; addr=0; end  // start
			if (cc == 1051) begin write_bus = 16'h00f2; addr=1; end  // tcn ckhi
			if (cc == 1101) begin write_bus = 16'h0247; addr=0; end  // data
			if (cc == 1151) begin write_bus = 16'h00b3; addr=1; end  // tcn trig
			if (cc == 2001) begin write_bus = 16'h0ffd; addr=0; end  // read/ack
			if (cc == 2051) begin write_bus = 16'h00b3; addr=1; end  // tcn trig
			if (cc == 3001) begin write_bus = 16'h0ffe; addr=0; end  // read/nack
			if (cc == 3051) begin write_bus = 16'h00b3; addr=1; end  // tcn trig
			if (cc == 4001) begin write_bus = 16'h00f2; addr=1; end  // tcn ckhi
			if (cc == 4051) begin write_bus = 16'h0400; addr=0; end  // stop
			clk = 0; #20;
		end
	end

	// really crude ADF4001
	reg [23:0] chip_sr = 0;
	reg PLL_MUXOUT;
	wire PLL_CLK, PLL_DATA, PLL_LE, PLL_CE;
	always @(posedge PLL_CLK) begin
		chip_sr <= {chip_sr[22:0], PLL_DATA};
		PLL_MUXOUT <= 1'bx;
		#20;
		PLL_MUXOUT = chip_sr[23];
	end

	wire [15:0] read_bus;
	wire SCLK, SDIN, DOUT1202, SDA75, CS1202, CS5742;
	sportx chip( clk, 
		addr, host_write, write_bus, read_bus,
        	SCLK, SDIN, DOUT1202, SDA75, CS1202, CS5742,
        	PLL_CLK, PLL_DATA, PLL_LE, PLL_MUXOUT, PLL_CE);

endmodule