Hello, my name is Larry.
I am a control freak.

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Following Moore's law, information processing follows the
trend:  rack -> chassis -> boards -> chips

But if you keep adding features (bloat) to a chassis or
board, instead of following Moore's law down, you end up
like the frog in the kettle.

Logical end-point -- any useful piece of Accelerator
control/instrumentation eventually ends up able to be implemented
on a chip.

Forseeable future still has divisions in chip Fab technology
between analog, digital, Flash, SDRAM, high voltage.  Some
convergence likely, but not all-in-one.

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Loaded question: in 2004-2005, when all the digital needs of
LLRF etc. will fit on a chip, will we "Just Do It"?  Or will
we have to navigate a minefield of interlocking single-vendor
intellectual property, where marketing departments of billion
dollar companies can "Just Say No"?

NanoEngine is my stepping stone to a "Just Do It" future.
All develpment investment is standards-based:  ANSI-C,
IEEE-1364 Verilog, IETF communications.  Actual implementations
includes support of proprietary components, but those components
are treated as commodities:
   * StrongARM   ->   any processor supported by GCC and Linux
   * i82559      ->   any documented Ethernet MAC chip
   * nanoEngine  ->   any embeddable, networked computer that
                      can read/write virtual registers

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We will end up with a single-chip FPGA/CPU.  Two subtly different
approaches, effectively compatible at the software level:
  1. Dedicated CPU integrated with FPGA:
       Altera Excalibur (ARM), Xilinx Virtex-II Pro (PPC), Atmel ...
  2. CPU implemented in FPGA fabric:
       Altera NIOS, Xilinx Microblaze, LEON SPARC, Jan Gray gr0040, ...

Communication Protocols (after all, this thing has to communicate
with the rest of the accelerator):
  Ethernet         -- 25 years old, stronger than ever
                      100 MBit/sec over twisted pair _or_ fiber
  FireWire         -- Intriguing, threatened with marginalization
  USB              -- Short distances only, agenda-driven
  OC-12,24,48,...  -- Intriguing transport, ATM looks like a mess to me

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Conclusions
   Keep It   Simple   Stupid
   Keep It    Small   Stupid
   Keep It  Standard  Stupid