P1 (50-pin) IP module host interface

P2 (50-pin) IP module user I/O
  1,2    Out1 return
  26     Out1 signal
  27,28  Out2 return
  3      Out2 signal
  4,29   GND
  5,30   In1
  6,31   GND
  7,32   In2
  8,33   GND
  9,34   In3
  10,35  GND
  11,36  In4
  12,37  GND
  13     SCLK
  38
  14     CS2#   (MAX1202)
  39
  15     DIN
  40
  16,41  GND
  17          shorted to GND, don't use
  42
  18     CS3#   (MAX1202)
  43
  19     RFON
  44     DOUT
  20,45  GND
  21     CS0#   (MAX528)
  46
  22     CS1#   (MAX528)
  47
  23
  48     KILL
  24,49  GND
  25
  50
(In1 through In4 have 1 V p-p full scale, or about +4 dBm.
They are transformer coupled (MiniCircuits T4-6T-KK81), so
there is a low frequency roll-off at about 20 kHz.)

J1 (160-pin Molex) nanoEngine

J2 (2 mm 5x2 header) Computer communications
  1  TX+     Eth-1
  2  TX-     Eth-2
  3  RX+     Eth-3
  4  RX-     Eth-6
  5  GND
  6  GND     Con-4   Con-6  PC-DB9-5
  7  CON_TX  Con-6   Con-5  PC-DB9-2
  8  CON_RX  Con-5   Con-4  PC-DB9-3
  9  MRST
 10  NC
(Eth-n and Con-n refer to RJ-45 pin numbers, where 1 is
on the left if you hold the plug with the tab away from
you, and the cable dangling down.)
(Final column of Con-x numbers correspond to final wiring,
adapted to match the Black-Box terminal server.)
(The placement of MRST adjacent to CON_RX is a mistake.
Trim pin 9 of any ribbon cables short, or else transmissions
to the nanoEngine (keystrokes) will capacitively couple to
MRST, and reset the nanoEngine.)

J3 (2 mm 5x2 header) JTAG
  1  TCK
  2  GND
  3  TDO
  4  VCC
  5  TMS
  6  MRST
  7  TRST
  8  WP
  9  TDI
 10  GND
(You can use this to check out the FPGA, but only if the
nanoEngine is unplugged, as would happen if you actually
plugged this board into an IP carrier.  Otherwise, software
on the nanoEngine will drive the FPGA with JTAG, and you
should leave this connector unused.)

J4 (2 mm 5x2 header) Utility input
  1  3.3V
  2  3.3V
  3  GND
  4  +5.0V
  5  +5.0V
  6  GND
  7  -12V
  8  CLK10
  9  GND
 10  CLK40

40 MHz clock "spec", nominal 50 Ohms input.
  Target is 0.5 V p-p at pin 3 of T1, or about -2 dBm.
  I get good results with 0.25 to 1.0 V p-p at this point.
  The ADC specifications call for 0.5V to 3.0V p-p, but
  large swings are dangerous to the chip if the clock
  is present when power is off.  The input is capacitive,
  so there is a fairly large reflection.  I hope to
  reduce the reflection on later boards.  Our boards
  are now modified to dedicate a coaxial cable for this
  signal, to reduce the coupling from CLK10 to this signal.
  CLK40 needs to be very phase stable (picoseconds of jitter)
  to get accurate conversions of the 50 MHz input signals.
10 MHz clock uses 3.3V CMOS levels, 5V TTL tolerant.
  This input can be ignored until multiple boards
  have to be synchronized.
3.3V input is for the nanoEngine, 600 mA max.
5.0V input is for the data acquisition, 600 mA max.
  (but much lower average, that's only during turnon
  and during data acquisition when the ADC's are
  brought out of sleep mode.)
  Can be supplied by this pin, or an IP carrier.
-12V input is on-board regulated to -5V for the
  bipolar DAC output (2xTHS4041), 30 mA max.
  Can be supplied by this pin, or an IP carrier.