Register map for LLRF FPGA, offset 0x40000000 in StrongARM memory map. All registers are 16 bits, but should be read and written as 32-bit quantities with the upper short unused. This is an artifact of using only 16 wires of a 32-bit muxed address/data bus. 0x0000 RO Product code 0x7701 0x0004 RO Firmware version code 19 0x0008 RO Status: lsb 0 gray_previous(0) 1 gray_previous(1) 2 gray_sample(0) 3 gray_sample(1) 4 urst 5 KCM_load_busy 6 SYNC 7 RF_ON 0x000c RO Errors (atomic clear on read): lsb 0 channel D overflow 1 channel C overflow 2 channel B overflow 3 channel A overflow 4 clk40_missing 5 ext_trigger_skipped 6 sync_missing 7 sync_error 0x0010 XX Number of pulses since last read of this register 0x0014 RO Counter at last trace buffer write 0x0018 XX 0x001c XX 0x0020 WO I setpoint (signed, 14 upper bits) 0x0024 WO Q setpoint (signed, 14 upper bits) 0x0028 WO Config: lsb 0 trace_enable 1 phase_sense_adjust 2 rising_edge_decay 3 continuous_feedforward 4 ignore_rf_off 5 self_retrigger 6 halt 7 trace_sel(0) 8 trace_sel(1) 9 feedback_select 10 integrate_select 11 test_point_enable 12 iq_hand_flip 13 dynamic_setpoint 0x002c WO trace buffer decimation: lsb 0 bit 2 is counter 2 vs. counter 10 1 bit 3 is counter 3 vs. counter 11 2 bit 4 is counter 4 vs. counter 12 3 bit 5 is counter 5 vs. counter 13 4 bit 6 is counter 6 vs. counter 14 5 bit 7 is counter 7 vs. counter 15 0x0030 WO KCM-real (signed, 12 upper bits) 0x0034 WO KCM-imag " 0x0038 WO KCM-integrator " 0x003c WO KCM-rise 0x0040 - 0x005c XX 0x0060 RW Serial ADC 1 transaction [3] 0x0064 RW Serial ADC 2 transaction [3] 0x0068 RW Serial DAC 1 transaction [4] 0x006c RW Serial DAC 2 transaction [4] 0x0070 - 0x007c XX 0x0080 RW length of state 1 (idle) [2a] 0x0084 RW time until end of state 7 (inhibit retrigger) [2b] 0x0088 RW length of state 3 (ADC warmup) [2a] 0x008c RW length of state 4 (feedforward only) [2a] 0x0090 RW length of state 5 (feedback) [2a] 0x0094 RW length of state 6 (acquire decay curve) [2a] 0x0098 RW unused 0x009c RW length of state 0 (wait for trigger) [2b] 0x00a0 - 0x00fc XX 0x0100 - 0x01fc XX stepper controller 0x3000 - 0x37fc RW 512x8 (1 BRAM) feedforward table 0x4000 - 0x4ffc RO 1024x12 (3 BRAM) decay buffer [5] 0x5000 - 0x7ffc XX 0x8000 - 0x8ffc RO 1024x11 (8/3 BRAM) channel A trace buffer 0x9000 - 0x9ffc XX 0xa000 - 0xaffc RO 1024x11 (8/3 BRAM) channel B trace buffer 0xb000 - 0xbffc XX 0xc000 - 0xcffc RO 1024x10 (8/3 BRAM) channel C trace buffer 0xd000 - 0xfffc XX XX -- not implemented RO -- Read Only WO -- Write Only RW -- Read and Write [2a] Time in units of 100 ns (4 40 MHz clock periods) [2b] Time in units of 400 ns (16 40 MHz clock periods) [3] Write 7 bits of MAX1202 configuration, Read 12 bits of ADC result and 1 bit of "cycle complete" [4] Write 16 bits of MAX528 configuration and data, Read 1 bit of "cycle complete" [5] Input channel selected by trace_sel in config register