library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity flasher is
    port (
	clk: in std_logic;
	err: in std_logic;
	lampo: out std_logic
    );
end flasher;

-- Flashes with 12.5% duty factor if err is present,
-- or 87.5% duty factor if err is not present.

architecture rtl of flasher is

-- total period of flashing is the combination of all three counters,
-- 11 + 10 + 3 = 24 bits
-- 25 MHz / 2^24 = 1.49 Hz
signal c1   : std_logic_vector (10 downto 0);
signal c1z  : std_logic;
signal c2   : std_logic_vector (9 downto 0);
signal c2z  : std_logic;
signal c3   : std_logic_vector (2 downto 0);
signal trip : std_logic;
signal lamp : std_logic;

begin

lampo <= lamp;
u1: process (clk) begin
  if (clk'event and clk = '1') then
	c1 <= c1 + 1;
	if (c1="00000000000") then
      c1z <= '1';
	else
      c1z <= '0';
	end if;
	if (c1z='1') then
		c2 <= c2 + 1;
	end if;
	if ((c1z='1') and (c2="0000000000")) then
      c2z <= '1';
	else
      c2z <= '0';
	end if;
	if (c2z='1') then
		c3 <= c3 + 1;
	end if;
	if (err='1') then
		trip <= '1';
	elsif (c2z='1' and c3="001") then
		trip <= '0';
	end if;
	if    (c2z='1' and c3="000") then
		lamp <= '1';
	elsif (c2z='1' and c3="001") then
		lamp <= not trip;
	elsif (c2z='1' and c3="111") then
		lamp <= '0';
	end if;
  end if;
end process u1;

end rtl;