library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

-- Dynamic Constant Coefficient Multiplier (dkcm) generated by the Core Generator has a latency of 
-- 16 Clk-cycles for reloading.  consult => http://www.xilinx.com/dsp/docs/dkcm.pdf

-- "reloadable" dynamic constant coefficient multiplier
entity KCM is	
  port (
       VAR     : in SIGNED (9 downto 0);
       CONST_K : in SIGNED (11 downto 0);    -- unsigned
       LOAD_K  : in STD_LOGIC;	             -- load constant, active high
       CLK     : in STD_LOGIC;
       BUSY    : out STD_LOGIC;
       PRODUCT : out SIGNED (21 downto 0)
       );
end KCM;

architecture KCM_usecore of KCM is

-- COMP_TAG
attribute black_box : boolean;   -- black-box declaration
component dkcms			 -- dkcms is created by the Core Generator 
  port (			 -- make sure dkcms.edn is in the same directory as the top-level design
	dataa   : in STD_LOGIC_VECTOR(9 downto 0);   -- variable
	signeda : in STD_LOGIC;			     -- sign of variable: HIGH = signed, LOW = unsigned
	datab   : in STD_LOGIC_VECTOR(11 downto 0);  -- constant, unsigned when generated
	loadb   : in STD_LOGIC;			     -- load constant 	
	c       : in STD_LOGIC;			     -- CLK
	busy    : out STD_LOGIC;		     -- high when constant is reloaded -> update the internal tables 
	product : out STD_LOGIC_VECTOR(21 downto 0)
       );
end component;
attribute black_box of dkcms : component is true;  -- to treat the component as a black box
-- COMP_TAG_END 

-- internal signals
signal iVAR     : STD_LOGIC_VECTOR (9 downto 0);
signal iCONST   : STD_LOGIC_VECTOR (11 downto 0);
signal iPRODUCT : STD_LOGIC_VECTOR (21 downto 0);
signal VAR_SIGN : STD_LOGIC;
signal nLOAD_K  : STD_LOGIC;

begin 
  iVAR     <= STD_LOGIC_VECTOR(VAR);
  iCONST   <= STD_LOGIC_VECTOR(CONST_K);
  -- iVAR <= "000000" & STD_LOGIC_VECTOR(VAR(3 downto 0));
  -- iCONST <= "000000000" & STD_LOGIC_VECTOR(CONST_K(2 downto 0));
  
  PRODUCT  <= SIGNED(iPRODUCT);
  VAR_SIGN <= '1';  -- signed
  -- nLOAD_K  <= not LOAD_K;  -- active low
    
  DKCM_1 : dkcms   
    port map (
              dataa   => iVAR,
	      signeda => VAR_SIGN,    
	      datab   => iCONST,
	      loadb   => LOAD_K,
	      busy    => BUSY,
	      c       => CLK,
	      product => iPRODUCT
	     );
end KCM_usecore;

-- synopsys translate_off

Library XilinxCoreLib;

-- synopsys translate_on

-- synopsys translate_off

-- ignored by synthesis process;  for simulation purpose only
configuration cfg_KCM of KCM is
  for KCM_usecore
    for all : dkcms use entity XilinxCoreLib.kdcm_v1_0(behavioral)
      generic map(
	  	  constant_datab  => CONST_K,
		  b_signed        => 1,		-- signed constant coefficient
		  registered      => 0,   	-- 1 = pipelined
		  constant_widthb => 12,	-- constant width
		  c_has_ce        => 0,		-- 0 = no CE
		  widtha          => 10		-- variable width
		 );	
     end for;
  end for;
end cfg_KCM;

-- synopsys translate_on

-- this is not the top-level design so in the next level up, the following text
-- should appear at the end of that file:
--
-- configuration <cfg> of <next_level> is
--     for <arch_name>
--           for all : dkcms use configuration cfg_dkcm;
--           end for;
--     end for;
-- end <cfg>;
--