-- automatically generated from perl ram.pl 16
-- Larry Doolittle   <ldoolitt@recycle.lbl.gov>  March 2002

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity RAM16X16S is
  port (
        A0:    in  std_logic;
        A1:    in  std_logic;
        A2:    in  std_logic;
        A3:    in  std_logic;
        D:     in  std_logic_vector(15 downto 0);
        O:     out std_logic_vector(15 downto 0);
        WCLK:  in  std_logic;
        WE:    in  std_logic
  );
end RAM16X16S;

architecture virtex of RAM16X16S is

component RAM16X1S is
  port (
        A0:    in  std_logic;
        A1:    in  std_logic;
        A2:    in  std_logic;
        A3:    in  std_logic;
        D:     in  std_logic;
        O:     out std_logic;
        WCLK:  in  std_logic;
        WE:    in  std_logic
  );
end component;

begin

bit0: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(0),
        O     => O(0),
        WCLK  => wclk,
        WE    => we
);

bit1: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(1),
        O     => O(1),
        WCLK  => wclk,
        WE    => we
);

bit2: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(2),
        O     => O(2),
        WCLK  => wclk,
        WE    => we
);

bit3: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(3),
        O     => O(3),
        WCLK  => wclk,
        WE    => we
);

bit4: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(4),
        O     => O(4),
        WCLK  => wclk,
        WE    => we
);

bit5: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(5),
        O     => O(5),
        WCLK  => wclk,
        WE    => we
);

bit6: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(6),
        O     => O(6),
        WCLK  => wclk,
        WE    => we
);

bit7: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(7),
        O     => O(7),
        WCLK  => wclk,
        WE    => we
);

bit8: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(8),
        O     => O(8),
        WCLK  => wclk,
        WE    => we
);

bit9: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(9),
        O     => O(9),
        WCLK  => wclk,
        WE    => we
);

bit10: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(10),
        O     => O(10),
        WCLK  => wclk,
        WE    => we
);

bit11: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(11),
        O     => O(11),
        WCLK  => wclk,
        WE    => we
);

bit12: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(12),
        O     => O(12),
        WCLK  => wclk,
        WE    => we
);

bit13: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(13),
        O     => O(13),
        WCLK  => wclk,
        WE    => we
);

bit14: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(14),
        O     => O(14),
        WCLK  => wclk,
        WE    => we
);

bit15: RAM16X1S port map (
        A0    => A0,
        A1    => A1,
        A2    => A2,
        A3    => A3,
        D     => D(15),
        O     => O(15),
        WCLK  => wclk,
        WE    => we
);

end virtex;