\documentclass[letterpaper]{article}
\usepackage{epsfig}

\begin{document}

\title{Plan for a 50\thinspace MHz Analog Output Channel}
\author{Lawrence R. Doolittle, LBNL}
\date{August 8, 2002}

\maketitle

To digitize a narrow band 50\thinspace MHz analog input, it is well
understood that one can cheat the normal Nyquist sampling rate rule.
While sampling at 200\thinspace MS/s will pull in sequential
I/Q/-I/-Q samples (suitable for clean vector manipulation)
such samples are also available when sampling at $200/(2n+1)$ MS/s.
The $n=2$ case, 40\thinspace MS/s, is used repeatedly in the SNS
project.  Of course, as $n$ increases, the analog input filter
must be made narrower and narrower to avoid unwanted aliasing.
This method works well because the analog bandwidth of modern
ADC chips is much higher than 1/4 their maximum sample rate;
the ADS808 used in the LBNL MEBT LLRF board has a maximum sample
rate of 70\thinspace MS/s, but an analog bandwidth of 1\thinspace GHz.

The converse problem, that of generating a narrow band 50\thinspace MHz waveform,
appears less well developed.  Certainly a 200\thinspace MS/s DAC would
work in theory, but as above, we would like to cheat and reduce
the update rate.  Such data rates are not plausible with
mid-range FPGAs, the selection of high resolution DAC chips is sparse,
the edge speeds required to drive the DAC are high and noisy,
and clock synchronization margins are tight.

One technique, used by
both the LBNL MEBT LLRF board and the LANL LLRF board, brings in a
separate 50\thinspace MHz source, which is vector modulated with signals from
twin, low data rate (20\thinspace MS/s) DACs.  Beyond the usual questions of channel
balance and phasing, the LBNL experience was that the particular
vector modulator used was rather nonlinear, and the extra 50\thinspace MHz
input wiring decreased reliability.

This note develops a design based on a direct synthesis technique,
using a data stream considerably slower than 200\thinspace MS/s.
As a lead-in to the final design, consider what happens if one feeds
I/Q/-I/-Q samples at 40\thinspace MS/s to a single high speed \hbox{DAC}.
The analog output will generate spectral lines not only at 10\thinspace MHz,
but at 10\thinspace MHz $\cdot~(2n+1)$.
Low order lines include 30\thinspace MHz, 50\thinspace MHz, and
70\thinspace MHz.  Power in these lines scales as $f^{-2}$, ignoring
the intrinsic DAC output filter ($\tau\sim 2$\thinspace ns for a DAC902).
Assuming +7\thinspace dBm total DAC output power,
and accounting for the use of an existing 50\thinspace MHz RLC output filter,
the power at the first few harmonics is:
\begin{center}
\begin{tabular}{rrrr}
 $f$ (MHz) &  $P_{\rm DAC}$\thinspace (dBm) &
 $A_{\rm filt}$\thinspace (dB) & $P_{\rm out}$\thinspace (dBm)\\
\input{table1.in}
\end{tabular}
\end{center}

Next, let's turn this concept into something more usable.
The 10\thinspace MHz, 70\thinspace MHz, and 90\thinspace MHz components
can be suppressed digitally by clocking the DAC at 80\thinspace MS/s
instead of 40\thinspace MS/s.  This rate is still
within the ``easy'' realm for mid-grade FPGAs and DACs.  The interpolation
logic within the FPGA can be fairly simple: given a string of 40\thinspace MS/s
data points, nominally representing $\pi/2$ phase advances in a 10\thinspace MHz waveform
   $$ \matrix{a_i, & a_{i+1}, & a_{i+2}, & ...\cr}$$
interleave with them points with the same amplitude, but a phase that
is interpolated to $-3\pi/4$.
   $$ \matrix{a_i, & -(a_i+a_{i+1})/\sqrt{2}, & a_{i+1}, & 
                    -(a_{i+1}+a_{i+2})/\sqrt{2}, & a_{i+2}, & ...\cr}$$
The resulting waveform nominally represents a 30\thinspace MHz sine wave, but
like the previous case includes a strong 50\thinspace MHz component.
An effective low-dispersion analog notch filter can be built from a delay
line and a splitter-recombiner pair, to suppress the 30\thinspace MHz component.
In concept:

\begin{center}
\mbox{\epsfig{file=notch-concept.eps,width=0.60\columnwidth}}
\end{center}

Combining the digital and analog filters, and assuming 3\% error
in notch frequency, the power flow now looks like this:

\begin{center}
\begin{tabular}{rrrrr}
 $f$ (MHz) &  $P_{\rm DAC}$\thinspace (dBm) &
 $A_{\rm notch}$\thinspace (dB) & $A_{\rm filt}$\thinspace (dB) & $P_{\rm out}$\thinspace (dBm)\\
\input{table2.in}
\end{tabular}
\end{center}
Compared to the 40\thinspace MS/s concept, this shows 7.5\thinspace dB
more signal at 50\thinspace MHz, and the largest sideband improves from
-49.5\thinspace dBc to -74.0\thinspace dBc.

The above description is relatively abstract; perhaps a graph of the
waveforms will make the concept more apparent.
The following figure shows the nominal
30\thinspace MHz output
of a perfect 80\thinspace MS/s DAC, the result of averaging that waveform
with a 16.7\thinspace ns delayed copy of itself, and the 50\thinspace MHz
component of that result.  Note that the waveforms repeat every 8 DAC samples,
or 100\thinspace ns.
\begin{center}
\mbox{\epsfig{file=f50.eps,width=0.90\columnwidth}}
\end{center}

The following circuit abandons the input splitter in favor of directly
driving a 25\thinspace $\Omega$ node with the high impedance output of the DAC,
where a 2:1 turns ratio transformer increases the effective impedance seen by the DAC
(differential mode) to 100\thinspace $\Omega$, a good match for the output compliance
of a DAC902.  Each output pin sources 0 to 20\thinspace mA of current, so the signal
strength is $\pm 10$\thinspace mA, and each pin delivers
${1\over 2}\cdot 10\thinspace{\rm mA} \cdot 0.5\thinspace{\rm V} = 2.5\thinspace\rm{mW}$
average power, totalling +7\thinspace dBm for the two pins.
The 30\thinspace MHz component of the DAC output is absorbed by the combiner.
The conventional 50\thinspace MHz RLC post filter is not shown.

\begin{center}
\mbox{\epsfig{file=oschem.eps,width=1.0\columnwidth}}
\end{center}

% Z=50
% t=3.3e-9
% L=t*Z
% C=t/Z
% A=.97
% R1=(1-A)/(1+A)*Z
% R2=1/(1/(Z-r1)-1/(Z+r1))

Since a 16.7\thinspace ns delay line is not available off-the-shelf,
the circuit employs a 20\thinspace ns part, and adds 3.3\thinspace ns
of compensating delay to the other leg.  An imbalanced 165\thinspace nH
inductor and a 66\thinspace pF capacitor add such a delay
in a 50\thinspace $\Omega$ system; the $\pi$
configuration shown uses capacitors of half that value.  R503 through
R505 are set up to balance the attenuation through the delay line,
nominally~3\%.  Depending on the amount of 30\thinspace MHz rejection
desired, one could hand select the components, install the nominal
values, or just line up three zero-ohm jumpers for R503, R505, and L501.

To start up a cold DTL tank, the controller needs to generate
output in the 50.0 to 50.4\thinspace MHz band.  This is readily accomplished
by a gradual, constant rate phase shift in the 10\thinspace MHz signal sent
to the interpolator and \hbox{DAC}.  Another description of the implementation
is a 400\thinspace kHz single sideband modulation of the carrier.
Successive 40\thinspace MS/s samples, that nominally show an
I/Q/-I/-Q pattern with $\pi/2$ phase advance between them, have 
their phase shift adjusted to $(1+\delta)\pi/2$, where to reach
10.4\thinspace MHz, $\delta$ can be as high as 0.04.  The interpolation
step described earlier multiplies the waveform by a 40\thinspace MHz carrier,
which turns the original 10.4\thinspace MHz into
29.6 and 50.4\thinspace MHz outputs.

The digital processing necessary to introduce controlled phase modulation
is well understood.  A high resolution phase accumulator is followed by
a CORDIC rotator.  Both are easily implemented in an FPGA; a 24-bit accumulator
plus a 12-bit accurate high-throughput rotator take up about 340 cells.
The current LBNL controller uses 40\% of the 3456 available in a Xilinx XC2S150.
The rotator introduces about 12 cycles (40 \thinspace MHz) of latency, which is
not an issue because the phase velocity will be constant during a macropulse,
and this block is outside the primary feedback loop.

Sideband modulation imbalances both the 30 MHz notch filter, and the digital
filter that suppresses the 10\thinspace MHz and 70\thinspace MHz lines.
These latter two lines will reappear
proportionally to $\delta$ -- calculations at 400\thinspace kHz modulation
show a 10.4\thinspace MHz spur at -29\thinspace dBc at the output of the 
notch filter, probably unmeasurable after the analog filter.
The 70\thinspace MHz component is even smaller.

In theory, one could change a handful of components (VCXO and delay), and
operate this circuit at 66/133\thinspace MHz instead of 40/80\thinspace MHz.
The notch filter moves from 30\thinspace MHz to 83.3 MHz\thinspace
(16.7\thinspace ns to 6.0\thinspace ns delay), and the divisors programmed
into the PLL chip (which locks the acquisition clock to the 50\thinspace MHz
phase reference) change.
The data sheets say that this is still within spec for the ADC, DAC, and PLL,
but the margins for these parts and the FPGA get mighty thin.
While the output power, output spectrum, and system latency would
all improve, the technical
risk is considered too high to pursue this option in the short term.
\end{document}
