Phase Locking for the SNS Event Link

One function needed throughout SNS is an Event Link receiver. The Event Link signal is broadcast site-wide over fibers and twisted pair, and provides the master synchronization to the storage ring revolution frequency, and therefore the chopping time structure on the linac beam current. LBNL instrumentation and control has several applications for the reconstructed clock signal, some of which require a low jitter clock, which runs at a large multiple (64) of the ring revolution rate. This note covers the analysis and design of the phase lock circuitry now under construction for a general purpose Event Link receiver in the form of an Industry Pack Module.

You may download this Tech note in its entirety in PostScript (321K) or PDF (98K). The PostScript version can be printed on any PostScript printer, or previewed with the Ghostscript suite. The PDF version can be viewed and printed using any of xpdf, the Ghostscript suite, or Adobe Acrobat (untested).

The code used for the simulations in the article can be downloaded: it consists of a Verilog main program, and a PLI module coded in c. These runs fine on Icarus Verilog, which in turn should run on any reasonable machine (Unix or Microsoft) with a c++ compiler.

You may download a kit (24K) that allows a complete regeneration of the note, including all simulation runs. This kit is tested on a Linux box with octave, Icarus Verilog, and LaTeX installed. Unpack it, and type "make" to get as far as the .dvi and .eps files. Other choices include "make print" and "make web".

You may look at the individual pieces, where all the figures are given in .eps form:

• LaTeX source file
• Figure 1. Block diagram of the system as modeled.
• Figure 2. Measured VCO jitter.
• Figure 3. VCO tuning characteristics.
  • part a. F vs. Vtune.
  • part b, F vs. dF/dV.
• Figure 6. System response vs. frequency.
• Figure 7. Symbol decode waveforms.
• Figure 8. Frequency locking transient.