// RAMB4_S8_S8.v
// Greatly simplified model of Xilinx dual port RAM
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

// simplifications compared to full model:
//    no INIT
//    no global reset
//    two ports are the same width
//    no treatment of collisions
`timescale 1ns / 1ns
(* ivl_synthesis_cell *)

module RAMB4_S8_S8 (DOA, DOB, ADDRA, CLKA, DIA, ENA, RSTA, WEA, ADDRB, CLKB, DIB, ENB, RSTB, WEB);

output [7:0] DOA,   DOB;
reg    [7:0] DOA,   DOB;
input  [7:0] DIA,   DIB;
input  [8:0] ADDRA, ADDRB;
input        CLKA,  CLKB,
             ENA,   ENB,
             WEA,   WEB,
             RSTA,  RSTB;
reg [7:0] memory[511:0];

always @(posedge CLKA) begin
	if (ENA) DOA <= RSTA ? 0 : (WEA ? DIA : memory[ADDRA]);
	if (ENA & WEA) memory[ADDRA] <= DIA;
end

always @(posedge CLKB) begin
	if (ENB) DOB <= RSTB ? 0 : (WEB ? DIB : memory[ADDRB]);
	if (ENB & WEB) memory[ADDRB] <= DIB;
end

endmodule