// SRL16E.v
// SRL16E model should be compatible with Xilinx's, but a whole lot tighter
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

`timescale 1ns / 1ns
(* ivl_synthesis_cell *)
... (truncated)
module SRL16E(Q, A0, A1, A2, A3, CE, CLK, D);
	parameter INIT=16'h0000;
	input  A0, A1, A2, A3, CE, CLK, D;
	output Q;
	reg [15:0] data;
	assign Q=data[{A3, A2, A1, A0}];
	initial
		data=INIT;
	always @(posedge CLK)
		if (CE == 1'b1) data[15:0] <= {data[14:0], D};
endmodule