// histmode.v
// Timing controller for one or more history buffers
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

// Initial coding: July 2003
// Synthesizable Verilog for Virtex-1/Spartan-2 (or better) target
// Each controlled history buffer is an instantiation of hist2.v.
`timescale 1ns / 1ns


module histmode(
	clk40, rst, trace_enable, average, stop_count,
	trace_address, write_enable, avg_clear, cnt_at_pulse_end);
parameter AVERAGE_BITS=`AVERAGE_BITS;
parameter ADDRESS_BITS=`ADDRESS_BITS;
input clk40, rst;     // Duh
input trace_enable;   // defines duration of valid input samples
input [AVERAGE_BITS-1:0] average;  // 0-127, (number of input samples per output bin)-1
input [14:0] stop_count;  // 0-32767, in input sample units
output [ADDRESS_BITS-1:0] trace_address;  // send to hist2.v
output write_enable, avg_clear; // send to hist2.v
output [14:0] cnt_at_pulse_end; // status report for host

reg  [14:0] cnt_at_pulse_end;
reg  [AVERAGE_BITS:0] countl;    // counts input samples within an averaging step
reg  [14:0] counth;   // counts output samples
wire [ADDRESS_BITS-1:0] trace_address = {counth[ADDRESS_BITS-2:0], countl[0:0]};
reg  write_squelch;

wire avg_clear = countl[AVERAGE_BITS:1] == 0;
wire carry = countl == {average, 1'b1};
assign write_enable = trace_enable & ~write_squelch;

always @(posedge clk40 or posedge rst) if (rst) begin
	countl <= 0;
	counth <= 0;
	cnt_at_pulse_end <= 0;
	write_squelch <= 0;
end else begin
	countl <= (carry | ~trace_enable) ? 0 : (countl + 1'b1);
	counth <= trace_enable ? (counth + carry) : 0;
	if (write_enable)
		cnt_at_pulse_end <= counth;
	if (~trace_enable | (carry && (counth == stop_count)))
		write_squelch <= trace_enable;
end

endmodule