// mult_bussed.v
// Ordinary signed multiplier, pin compatible with DKCM version
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

// Useful if the FPGA has dedicated multipliers, like the Xilinx V2

`timescale 1ns / 1ns


module dkcm_bussed(
	input  [11:0] var,
	output [23:0] product,
	input         clk,
	input  [21:0] dkcm_bus,
	input   [2:0] ident
);

wire [15:0] load_data = dkcm_bus[20:5];
wire  [2:0] load_addr = dkcm_bus[4:2];
wire        load      = dkcm_bus[0] & (load_addr == ident);

reg signed [11:0] konstant;
always @(posedge clk) begin
	if (load) konstant <= load_data[15:4];
end

wire signed [11:0] svar = var;
wire signed [23:0] sproduct = konstant * svar;
assign product=sproduct;

endmodule