// shadow_ram.v
// LLRF shadow RAM
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

`timescale 1ns / 1ns


module shadow_ram(
	input host_clk, // interconnect
	input host_we,  // interconnect
	input  [13:0] host_addr,   // interconnect
	input select,   // select SHADOW
	input  [15:0] host_data,   // interconnect
	output [15:0] read_bus     // register SHADOW
);

reg [15:0] ram[31:0];
assign read_bus = ram[host_addr[4:0]];
always @(posedge host_clk) if (host_we & select)
	ram[host_addr[4:0]] <= host_data;

endmodule