// sync_free.v
// Free running 10 MHz divider
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

// Interconnect-compatible with sync_mebt.v,
// but without the MEBT-style "sync-to-external-10MHz-clock" feature.
// Relative phase is determined in software
// by digitizing the analog 50 MHz phase reference.

`timescale 1ns / 1ns


module sync_free(
	input clk40,                 // interconnect
	output quad_sync,            // interconnect
	output sync_error,           // interconnect
	output sync_missing          // interconnect
);

assign sync_error = 0;
assign sync_missing = 0;

reg [1:0] sync_count;
`ifdef SIMULATE
initial sync_count = 0;
`endif

always @(posedge clk40) sync_count <= sync_count + 1'b1;
assign quad_sync = (sync_count == 2'b11);

endmodule