// afterdemux.v
// I/Q demux for AD9765 baseband output channel pair
// $Id$
// Larry Doolittle, LBNL

// llc-suite Copyright (c) 2004, The Regents of the University of
// California, through Lawrence Berkeley National Laboratory (subject
// to receipt of any required approvals from the U.S. Dept. of Energy).
// All rights reserved.

// Your use of this software is pursuant to a "BSD-style" open
// source license agreement, the text of which is in license.txt
// (md5sum a1e0e81c78f6eba050b0e96996f49fd5) that should accompany
// this file.  If the license agreement is not there, or if you
// have questions about the license, please contact Berkeley Lab's
// Technology Transfer Department at TTD@lbl.gov referring to
// "llc-suite (LBNL Ref CR-1988)"

// Input (outsig40) comes in clocked by clk40
// Input is signed.  Output to the AD9765 is unsigned.

`timescale 1ns / 1ns


module afterdemux(
	input clk40,                  // interconnect
	input host_clk,               // interconnect
	input [15:0] mode_control,    // register AFTER_CFG
	input [11:0] outsig40,        // interconnect
	output [11:0] DE,             // pin b
	output OCLK,                  // pin d
	output OSEL                   // pin e
);

wire iq_hand_flip = mode_control[0];
wire [1:0] sync_count = 0;  // XXX just plain wrong
assign OCLK = ~clk40;
assign OSEL = sync_count[0] ^ iq_hand_flip;
assign DE = {~outsig40[11], outsig40[10:0]} ^ {12{sync_count[1]}};

endmodule