This is the latest (and greatest!) in a long series of fully-unrolled CORDIC processors written by Larry Doolittle, with occasional help from Ming Choy and Gang Huang. It is written in portable Verilog, synthesizable for pretty much any FPGA; part of that Verilog is in turn composed by a Python program.
CORDIC performance for 18 bit data and 20 stages

Latest README file; and the license based on 3-clause BSD.

Tarballs (newest to oldest):

Good reference material on CORDIC hardware is given by Ray Andraka

Happy computing!

Larry Doolittle
Mar 12, 2020