This packet is "source code" to accompany the monograph Digital IQ Reconstruction from a non-IQ Sampled Waveform Larry Doolittle, LBNL, November 2008 Type "make" on a modern Linux computer with Octave and Icarus Verilog installed to run all the test benches and regenerate the paper with its figures. The actual synthesizable Verilog code that is ready to apply to LLRF projects is cav_input.v, and its sub-modules cordicg.v, downconvert.v, and sat_sub.v. Type "make syn_test" to run a test synthesis of these modules for a Spartan-3 chip using Xilinx ISE. You should also look at cav_input_tb.v for an instantiation example. A section of that code, shared across multiple instantiations of cav_input.v, is intended to be incorporated in the encapsulating FPGA code. The only sub-module of that code is rat_dds.v. Good luck! - Larry Doolittle